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IDT54FCT2543TEB

更新时间： 2024-11-05 23:11:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
7页 123K
描述
FAST CMOS OCTAL LATCHED TRANSCEIVER

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中文翻译

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IDT54FCT2543TEB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：CERPACK-24
针数：24Reach Compliance Code：not_compliant
风险等级：5.92其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; MASTER CONTROL FOR LATCH
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：FCTJESD-30 代码：R-GDFP-F24
JESD-609代码：e0长度：15.748 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.012 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装等效代码：FL24,.4
封装形状：RECTANGULAR封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：10 ns传播延迟（tpd）：14 ns
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：2.286 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：9.144 mmBase Number Matches：1

IDT54FCT2543TEB 数据手册

 浏览型号IDT54FCT2543TEB的Datasheet PDF文件第2页浏览型号IDT54FCT2543TEB的Datasheet PDF文件第3页浏览型号IDT54FCT2543TEB的Datasheet PDF文件第4页浏览型号IDT54FCT2543TEB的Datasheet PDF文件第5页浏览型号IDT54FCT2543TEB的Datasheet PDF文件第6页浏览型号IDT54FCT2543TEB的Datasheet PDF文件第7页 
IDT54/74FCT543T/AT/CT/DT  
IDT54/74FCT2543T/AT/CT  
FAST CMOS  
OCTAL LATCHED  
TRANSCEIVER  
Integrated Device Technology, Inc.  
FEATURES:  
• Common features:  
– Low input and output leakage ≤1µA (max.)  
– CMOS power levels  
– True TTL input and output compatibility  
– VOH = 3.3V (typ.)  
DESCRIPTION:  
The FCT543T/FCT2543T is a non-inverting octal trans-  
ceiver built using an advanced dual metal CMOS technology.  
This device contains two sets of eight D-type latches with  
separate input and output controls for each set. For data flow  
fromAtoB, forexample, theA-to-BEnable(CEAB)inputmust  
be LOW in order to enter data from A0–A7 or to take data from  
B0–B7, as indicated in the Function Table. With CEAB LOW,  
a LOW signal on the A-to-B Latch Enable (LEAB) input makes  
the A-to-B latches transparent; a subsequent LOW-to-HIGH  
transition of the LEAB signal puts the A latches in the storage  
mode and their outputs no longer change with the A inputs.  
With CEAB and OEAB both LOW, the 3-state B output buffers  
are active and reflect the data present at the output of the A  
latches. Control of data from B to A is similar, but uses the  
CEBA, LEBA and OEBA inputs.  
– VOL = 0.3V (typ.)  
– Meets or exceeds JEDEC standard 18 specifications  
– Product available in Radiation Tolerant and Radiation  
Enhanced versions  
– Military product compliant to MIL-STD-883, Class B  
and DESC listed (dual marked)  
– Available in DIP, SOIC, SSOP, QSOP, CERPACK  
and LCC packages  
• Features for FCT543T:  
– Std., A, C and D speed grades  
– High drive outputs (-15mA IOH, 64mA IOL)  
– Power off disable outputs permit “live insertion”  
• Features for FCT2543T:  
– Std., A, and C speed grades  
– Resistor outputs (-15mA IOH, 12mA IOL Com.)  
(-12mA IOH, 12mA IOL Mil.)  
The FCT2543T has balanced output drive with current  
limiting resistors. This offers low ground bounce, minimal  
undershoot and controlled output fall times-reducing the need  
for external series terminating resistors. FCT2xxxT parts are  
plug-in replacements for FCTxxxT parts.  
– Reduced system switching noise  
FUNCTIONAL BLOCK DIAGRAM  
DETAIL A  
B0  
D
Q
LE  
Q
D
A0  
LE  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
B5  
DETAIL A x 7  
B6  
B7  
OEBA  
OEAB  
CEBA  
LEBA  
CEAB  
LEAB  
2613 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
JANUARY 1995  
1995 Integrated Device Technology, Inc.  
6.17  
DSC-4203/5  
1
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