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IDT10496RL12C PDF预览

IDT10496RL12C

更新时间: 2024-09-28 20:24:19
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
8页 169K
描述
Standard SRAM, 16KX4, 12ns, CDIP32

IDT10496RL12C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.92
最长访问时间:12 nsI/O 类型:SEPARATE
JESD-30 代码:R-CDIP-T32JESD-609代码:e0
内存密度:65536 bit内存集成电路类型:STANDARD SRAM
内存宽度:4负电源额定电压:-5.2 V
功能数量:1端子数量:32
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX4
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP32,.4封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:-5.2 V
认证状态:Not Qualified子类别:SRAMs
最大压摆率:0.26 mA表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

IDT10496RL12C 数据手册

 浏览型号IDT10496RL12C的Datasheet PDF文件第2页浏览型号IDT10496RL12C的Datasheet PDF文件第3页浏览型号IDT10496RL12C的Datasheet PDF文件第4页浏览型号IDT10496RL12C的Datasheet PDF文件第5页浏览型号IDT10496RL12C的Datasheet PDF文件第6页浏览型号IDT10496RL12C的Datasheet PDF文件第7页 
IDT10496RL  
IDT100496RL  
IDT101496RL  
SELF-TIMED BiCMOS ECL  
STATIC RAM  
64K (16K x 4-BIT) STRAM  
Integrated Device Technology, Inc.  
and latches on outputs, and the self-timed write operation,  
provide enhanced system performance over conventional  
RAMs, providing easier design and improved system level  
cycle times.  
FEATURES:  
• 16,384-words x 4-bit organization  
• Self-Timed, with registers on inputs and latches on  
outputs  
Inputs are captured by the leading edge of an externally  
supplied differential clock. The small input valid window re-  
quiredmeansmoremarginforsystemskews.Logic-to-memory  
propagation delay is included in device cycle time calculation,  
allowingthisdevicetodeliverbettersystemperformancethan  
asynchronous SRAMs and glue logic.  
• Balanced Read/Write cycle time: 10/12/15 ns  
• Access time: 10/12/15 ns (max.)  
• Fully compatible with ECL logic levels  
• Through-hole DIP and surface-mount packages  
DESCRIPTION:  
Write timing is controlled internally based on the clock.  
Write Enable has no special requirements. The device allows  
balancedreadandwritecycletimes, andreadsandwritescan  
be inserted in any order.  
The IDT10496RL, IDT100496RL and IDT101496RL are  
65,536-bit high-speed BiCEMOS ECL static random ac-  
cess memories organized as 16K x 4, with inputs and outputs  
fully compatible with ECL levels. Clocked registers on inputs  
FUNCTIONAL BLOCK DIAGRAM  
A0  
R
E
G
I
65,536-BIT  
MEMORY ARRAY  
V
V
CC  
EE  
DECODER  
S
T
E
R
REF. VOLTAGE  
GENERATOR  
V
BB  
A13  
R
E
G
I
S
T
E
R
D
0
Q
Q
Q
Q
0
1
2
3
L
A
T
C
H
SENSE AMPS  
AND READ/WRITE  
CONTROL  
D1  
A
D2  
D3  
WRITE-PULSE  
GENERATOR  
*
MUX  
B
A/B  
L
A
T
C
H
R
E
G
WE  
CS  
2771 drw 01  
CLK  
CLK  
* *HOLD/OPEN  
BiCEMOS is a trademark of Integrated Device Technology, Inc.  
COMMERCIAL TEMPERATURE RANGE  
AUGUST 1992  
1992 Integrated Device Technology, Inc.  
1

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