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ID82C85

更新时间： 2024-11-05 20:23:59
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟外围集成电路晶体
页数 文件大小 规格书
20页 169K
描述
Processor Specific Clock Generator

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中文翻译

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ID82C85 技术参数

生命周期：Active包装说明：,
Reach Compliance Code：compliant风险等级：5.8
JESD-30 代码：R-CDIP-T24端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：8 MHz封装主体材料：CERAMIC, GLASS-SEALED
封装形状：RECTANGULAR主时钟/晶体标称频率：25 MHz
最大压摆率：70 mA最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子位置：DUALuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

ID82C85 数据手册

 浏览型号ID82C85的Datasheet PDF文件第2页浏览型号ID82C85的Datasheet PDF文件第3页浏览型号ID82C85的Datasheet PDF文件第4页浏览型号ID82C85的Datasheet PDF文件第5页浏览型号ID82C85的Datasheet PDF文件第6页浏览型号ID82C85的Datasheet PDF文件第7页 
82C85  
CMOS Static Clock Controller/Generator  
March 1997  
Features  
Description  
• Generates the System Clock For CMOS or NMOS  
Microprocessors and Peripherals  
The Intersil 82C85 Static CMOS Clock Controller/Genera-  
tor provides complete control of static CMOS system oper-  
ating modes and supports full speed, slow, stop-clock and  
stop-oscillator operation. While directly compatible with the  
Intersil 80C86 and 80C88 16-bit Static CMOS Microproces-  
sor Family, the 82C85 can also be used for general system  
clock control.  
• Complete Control Over System Operation for Very  
Low System Power  
- Stop-Oscillator  
- Low Frequency  
- Stop-Clock  
For static system designs, separate signals are provided on  
the 82C85 for stop (S0, S1, S2/STOP) and start (START)  
control of the crystal oscillator and system clocks. A single  
control line (SLO/FST) determines 82C85 fast (crystal/EFI  
frequency divided by 3) or slow (crystal/EFI frequency  
divided by 768) mode operation. Automatic maximum  
mode 80C86 and 80C88 software HALT instruction decode  
logic in the 82C85 enables software-based clock control.  
Restart logic insures valid clock start-up and complete syn-  
chronization of system clocks.  
- Full Speed Operation  
• DC to 25MHz Operation (DC to 8MHz System Clock)  
• Generates 50% and 33% Duty Cycle Clocks  
(Synchronized)  
• Uses a Parallel Mode Crystal Circuit or External  
Frequency Source  
• TTL Compatible Inputs/Outputs  
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC  
Package Options  
The 82C85 is manufactured using the Intersil advanced  
Scaled SAJI IV CMOS process. In addition to clock control  
circuitry, the 82C85 also contains a crystal controlled  
• Single 5V Power Supply  
• Operating Temperature Range  
o
o
- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C oscillator (up to 25MHz), clock generation logic, complete  
o
o
“Ready” synchronization and reset logic. This permits the  
designer to tailor the system power-performance product to  
provide optimum performance at low power levels.  
- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C  
o
o
- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C  
Ordering Information  
PART NUMBER  
PACKAGE  
TEMP. RANGE PKG. NO.  
o
o
CS82C85  
28 Ld PLCC  
0 C to +70 C  
N28.45  
o
o
IS82C85  
-40 C to +85 C N28.45  
o
o
CD82C85  
24 Ld CERDIP  
0 C to +70 C  
F24.3  
o
o
ID82C85  
-40 C to +85 C F24.3  
o
o
MD82C85/B  
MR82C85/B  
-55 C to +125 C F24.3  
o
o
28 Pad CLCC -55 C to +125 C J28.A  
Pinouts  
24 LEAD CERDIP  
28 LEAD PLCC, CLCC  
TOP VIEW  
TOP VIEW  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CSYNC  
V
CC  
PCLK  
AEN1  
X1  
3
4
3
2
28 27 26  
1
X2  
25  
24  
23  
22  
21  
20  
19  
NC  
ASYNC  
EFI  
RDY1  
READY  
RDY2  
AEN2  
CLK  
5
6
7
8
9
4
ASYNC  
EFI  
RDY1  
5
READY  
RDY2  
6
F/C  
F/C  
7
AEN2  
OSC  
RES  
RESET  
S2/STOP  
S1  
OSC  
RES  
RESET  
8
CLK  
GND 10  
NC 11  
9
GND  
12 13 14 15  
17  
18  
16  
10  
11  
12  
CLK50  
START  
SLO/FST  
S0  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2976.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19949-297  
1234567...20

中文翻译

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