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ICS954101DFLF PDF预览

ICS954101DFLF

更新时间: 2024-11-11 14:42:43
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
17页 191K
描述
Processor Specific Clock Generator, 400MHz, PDSO56, 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56

ICS954101DFLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.19
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:18.43 mm湿度敏感等级:1
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:400 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.8 mm
子类别:Clock Generators最大压摆率:500 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS954101DFLF 数据手册

 浏览型号ICS954101DFLF的Datasheet PDF文件第2页浏览型号ICS954101DFLF的Datasheet PDF文件第3页浏览型号ICS954101DFLF的Datasheet PDF文件第4页浏览型号ICS954101DFLF的Datasheet PDF文件第5页浏览型号ICS954101DFLF的Datasheet PDF文件第6页浏览型号ICS954101DFLF的Datasheet PDF文件第7页 
Integrated  
Circuit  
ICS954101  
Systems, Inc.  
Programmable Timing Control Hub™ for Desktop P4™ Systems  
Recommended Application:  
Features/Benefits:  
CK410 clock, Intel Yellow Cover part  
Supports tight ppm accuracy clocks for Serial-ATA and  
PCI-Express  
Output Features:  
Supports spread spectrum modulation, 0 to -0.5%  
down spread  
2 - 0.7V current-mode differential CPU pairs  
6 - 0.7V current-mode differential SRC pair for SATA and  
PCI-E  
Supports CPU clks up to 400MHz  
Uses external 14.318MHz crystal, external crystal load  
caps are required for frequency tuning  
1 - 0.7V current-mode differential CPU/SRC selectable  
pair  
Supports undriven differential CPU, SRC pair in PD#  
for power management.  
6 - PCI (33MHz)  
3 - PCICLK_F, (33MHz) free-running  
1 - USB, 48MHz  
1 - DOT, 96MHz, 0.7V current differential pair  
1 - REF, 14.318MHz  
Key Specifications:  
CPU outputs cycle-cycle jitter < 85ps  
SRC output cycle-cycle jitter <125ps  
PCI outputs cycle-cycle jitter < 500ps  
+/- 300ppm frequency accuracy on CPU & SRC clocks  
Functionality  
Pin Configuration  
CPU  
MHz  
SRC  
MHz  
PCI  
MHz  
REF  
MHz  
USB  
MHz  
DOT  
MHz  
FS_C1 FS_B2 FS_A2  
VDDPCI 1  
GND 2  
PCICLK3 3  
PCICLK4 4  
PCICLK5 5  
56 PCICLK2  
55 PCICLK1  
54 PCICLK0  
53 FS_C/TEST_SEL  
52 REFOUT  
51 GND  
50 X1  
49 X2  
48 VDDREF  
47 SDATA  
46 SCLK  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266.66  
133.33  
200.00  
166.66  
333.33  
100.00  
400.00  
100.00 33.33 14.318  
100.00 33.33 14.318  
100.00 33.33 14.318  
100.00 33.33 14.318  
100.00 33.33 14.318  
100.00 33.33 14.318  
100.00 33.33 14.318  
48.00  
48.00  
48.00  
48.00  
48.00  
48.00  
48.00  
48.00  
96.00  
96.00  
96.00  
96.00  
96.00  
96.00  
96.00  
96.00  
0
0
0
0
1
1
1
1
GND 6  
VDDPCI 7  
ITP_EN/PCICLK_F0 8  
PCICLK_F1 9  
PCICLK_F2 10  
VDD48 11  
RESERVED  
14.318  
FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in  
the Input/Supply/Common Output Parameters Table for correct values.  
Also refer to the Test Clarification Table.  
2. FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS  
specifications in the Input/Supply/Common Output Parameters Table for correct values.  
1.  
USB_48MHz 12  
GND 13  
45 GND  
44 CPUCLKT0  
43 CPUCLKC0  
42 VDDCPU  
41 CPUCLKT1  
40 CPUCLKC1  
39 IREF  
DOTT_96MHz 14  
DOTC_96MHz 15  
FS_B/TEST_MODE 16  
Vtt_PwrGd#/PD 17  
FS_A_410 18  
SRCCLKT1 19  
SRCCLKC1 20  
VDDSRC 21  
SRCCLKT2 22  
SRCCLKC2 23  
SRCCLKT3 24  
SRCCLKC3 25  
SRCCLKT4_SATA 26  
SRCCLKC4_SATA 27  
VDDSRC 28  
38 GNDA  
37 VDDA  
36 CPUCLKT2_ITP/SRCCLKT_7  
35 CPUCLKC2_ITP/SRCCLKC_7  
34 VDDSRC  
33 SRCCLKT6  
32 SRCCLKC6  
31 SRCCLKT5  
30 SRCCLKC5  
29 GND  
56-pin SSOP & TSSOP  
0815G—12/02/08  

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