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ICS950201AFLFT PDF预览

ICS950201AFLFT

更新时间: 2024-02-06 05:46:54
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
15页 200K
描述
Processor Specific Clock Generator, 200MHz, PDSO56, 0.300 INCH, GREEN, MO-118, SSOP-56

ICS950201AFLFT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.18
Is Samacsys:NJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:18.43 mm
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.8 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

ICS950201AFLFT 数据手册

 浏览型号ICS950201AFLFT的Datasheet PDF文件第2页浏览型号ICS950201AFLFT的Datasheet PDF文件第3页浏览型号ICS950201AFLFT的Datasheet PDF文件第4页浏览型号ICS950201AFLFT的Datasheet PDF文件第5页浏览型号ICS950201AFLFT的Datasheet PDF文件第6页浏览型号ICS950201AFLFT的Datasheet PDF文件第7页 
DATASHEET  
Programmable Timing Control HubTM for P4TM  
ICS950201  
Frequency Table  
Recommended Application:  
CK-408 clock for Intel® 845 chipset with P4 processor.  
Output Features:  
66Buff[2:0]  
PCI_F  
PCI  
CPU  
FS2 FS1 FS0  
(MHz)  
3V66  
3V66[4:2]  
(MHz)  
(MHz)  
(MHz)  
3 Differential CPU Clock Pairs @ 3.3V  
7 PCI (3.3V) @ 33.3MHz  
3 PCI_F (3.3V) @ 33.3MHz  
1 USB (3.3V) @ 48MHz  
1 DOT (3.3V) @ 48MHz  
1 REF (3.3V) @ 14.318MHz  
5 3V66 (3.3V) @ 66.6MHz  
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
66.66  
100.00  
200.00  
133.33  
Tristate  
66.66  
66.66  
66.66  
66.66  
Tristate  
66.66  
66.66  
33.33  
33.33  
0
66.66  
33.33  
0
66.66  
33.33  
Mid  
Mid  
Mid  
Mid  
Tristate  
TCLK/4  
Tristate  
TCLK/8  
TCLK/2 TCLK/4  
Reserved Reserved Reserved Reserved  
Reserved Reserved Reserved Reserved  
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz  
Features:  
Supports spread spectrum modulation,  
down spread 0 to -0.5%.  
Efficient power management scheme through PD#,  
CPU_STOP# and PCI_STOP#.  
Uses external 14.318MHz crystal  
Stop clocks and functional control available through  
I2C interface.  
Key Specifications:  
CPU Output Jitter <150ps  
3V66 Output Jitter <250ps  
CPU Output Skew <100ps, programmable over 800 ps  
with groups CPU0,1 and CPU2.  
Pin Configuration  
56-Pin SSOP & TSSOP  
* These inputs have 150K internal pull-up resistor to VDD.  
IDTTM Programmable Timing Control HubTM for P4TM  
460J—01/25/10  
1

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