Integrated
Circuit
ICS950208
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
Pin Configuration
CK-408 clock with driven mode only for Brookdale chipset with
P4 processor.
*MULTSEL1/REF1 1
48 REF0/MULTSEL0*
GNDREF
VDDREF 2
47
46 VDDCPU
CPUCLKT2
Output Features:
X1 3
X2 4
45
•
•
•
•
•
•
3 - Pairs of differential CPU clocks @ 3.3V
4 - 3V66 @ 3.3V
10 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz selectable output @ 3.3V
2 - REF @ 3.3V, 14.318MHz
GND 5
44 CPUCLKC2
43 GNDCPU
42 PD#
*FS2/PCICLK_F0 6
*FS3/PCICLK_F1 7
PCICLK_F2 8
VDDPCI 9
41
CPUCLKT0
40 CPUCLKC0
VDDCPU
*FS4/PCICLK0 10
PCICLK1 11
PCICLK2 12
GND 13
39
38
37
36
CPUCLKT1
CPUCLKC1
GNDCPU
Features/Benefits:
•
•
•
•
•
•
Programmable output frequency.
PCICLK3 14
PCICLK4 15
PCICLK5 16
PCICLK6 17
VDDPCI 18
Vttpwr_GD# 19
RESET# 20
GND 21
35 IREF
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
34 AVDD
33 GND
32 VDD3V66
31 3V66_0
3V66_1
GND
30
29
28
27
3V66_2
3V66_3
*FS0/48MHz 22
*FS1/24_48MHz 23
AVDD48 24
•
•
Programmable watch dog safe frequency.
Supports I2C Index read/write and block read/write
operations.
26 SCLK
25 SDATA
48-SSOP
* Internal Pull-Up Resistor of 120K to VDD
•
Uses external 14.318MHz crystal.
Key Specifications:
Frequency Table
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
CPU
MHz
3V66
MHz
PCI
Bit2
Bit7
Bit6
Bit5
Bit4
FS4
FS3
FS2
FS1
FS0
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
102.00
105.00
108.00
111.00
114.00
117.00
120.00
68.00
70.00
72.00
74.00
76.00
78.00
80.00
34.00
35.00
36.00
37.00
38.00
39.00
40.00
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
123.00
126.00
130.00
136.00
140.00
144.00
148.00
152.00
156.00
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
82.00
72.00
74.30
68.00
70.00
72.00
74.00
76.00
78.00
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
66.80
66.80
66.80
66.60
66.60
66.60
66.60
41.00
36.00
37.10
34.00
35.00
36.00
37.00
38.00
39.00
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.40
33.40
33.40
33.30
33.30
33.30
33.30
Block Diagram
PLL2
48MHz
24_48MHz
REFF ((11::00))
0
0
1
1
1
1
1
1
0
1
/ 2
X1
X2
XTAL
OSC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL1
Spread
Spectrum
CPUUCCLLKKTT ((22::00))
CPPUUCCLLKKCC ((22::00))
CPPUU
DIIVVDDEERR
3
3
PCCII
DIIVVDDEERR
10 PCIICLK (6:0), PCICLK_F (1:0)
Conttrrooll
Logicc
PD#
MULTSEL(1:0)
FS (4:0))
3VV6666
DIIVVDDEERR
3V66 (33::00))
4
100.20
133.60
200.40
66.60
SDATA
RESSEETT##
I REFF
Conffiigg..
Reegg..
SSCCLLK
Vtt_PWRGD#
100.00
200.00
133.33
1
1
1
1
1
1
1
1
0
1
0464B—08/04/03