Datasheet > ICS9250F-24

ICS9250F-24

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	83K
描述
Clock Generator

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中文翻译

获取价格

数据手册

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ICS9250F-24 数据手册

ICS9250-24

Integrated

Circuit

Systems, Inc.

Integrated Buffers for PIII™

Recommended Application:

General purpose peripheral clk gen, also for IA64.

Pin Configuration

GND

14.318_IN

VDD

66_IN

GND

PCICLK0

PCICLK1

VDD

REF-1

REF-0

GND

Output Features:

•

12 - PCI clocks @ 3V

2 - 48MHz clocks

6 - 3V66 66MHz reference output

2 - 14.318 reference output

VDD

3V66-5

3V66-4

GND

PCICLK2

PCICLK3

VDD

3V66-3

3V66-2

VDD

Features:

•

Effective power management scheme through PD#

14.318MHz reference input

66MHz reference input

GND

VDD

PCICLK4

PCICLK5

VDD

PCICLK6

PCICLK7

GND

3V66-1

3V66-0

GND

VDD

GND

AVDD

48MHz-1

48MHz-0

AGND

FS2

PD#

VDD

GND

SCLK

SDATA

Key Specifications:

•

48MHz Output Jitter: <350ps

3V66 to PCI Skew: 1.5 to 3.5ns

PCI to PCI Skew: <500ps

VDD

PCICLK8

PCICLK9

GND

PCICLK10

PCICLK11

VDD

3V66 to 3V66 Skew: <250ps

FS0

FS1

56-Pin 300mil SSOP &TSSOP

Block Diagram

Functionality

FS0 FS1 FS2

Description

Details

All outputs on All outputs on

14.318_IN

REF (1:0)

Pins 18, 17, 15, 14, 11,

PCI (7:0) off

10, 7, 6 held LOW

PLL

48MHz (1:0)

Pins 15, 14, 11, 10, 7, 6

held LOW

PCI (5:0) off

All PCI off

Tristate

Control

SDATA

All PCI outputs held LOW

Logic

SCLK

All outputs high

impedance

FS (2:0)

Config.

PD#

3V66-5 off

Pin 51 held LOW

Reg.

REF (1:0) off Pins 55, 54 held LOW

48MHz-1 off Pin 37 held LOW

66_IN

3V66 (5:0)

Delay

PCICLK (11:0)

/ 2

Power Groups

AGND = Analog ground

AVDD = Analog power

0390C—11/06/02

12 3 4 5 6 7...9

中文翻译

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