Datasheet > ICS8745BMI-21T

ICS8745BMI-21T

更新时间： 2024-10-01 05:13:51

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
19页	321K
描述
PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2.30 MM HEIGHT, MO-119, SOIC-20

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ICS8745BMI-21T 数据手册

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY

CLOCK GENERATOR

ICS8745BI-21

Description

Features

The ICS8745BI-21 is a highly versatile 1:1 LVDS

• One differential LVDS output designed to meet

or exceed the requirements of ANSI TIA/EIA-644

One differential feedback output pair

Clock Generator and a member of the HiPerClockS™

f family of High Performance Clock Solutions from

IDT. The ICS8745BI-21 has a fully integrated PLL

and can be configured as zero delay buffer,

HiPerClockS™

• Differential CLK, CLK input pair

• CLKx, CLKx pair can accept the following differential

multiplier or divider, and has an output frequency range of

31.25MHz to 700MHz. The Reference Divider, Feedback Divider

and Output Divider are each programmable, thereby allowing for

the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8. The external feedback allows the device to achieve

“zero delay” between the input clock and the output clock. The

PLL_SEL pin can be used to bypass the PLL for system test and

debug purposes. In bypass mode, the reference clock is routed

around the PLL and into the internal output dividers.

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 30ps (maximum)

• Output skew: 40ps (maximum)

• Static phase offset: 25ps ± 125ps

• Full 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Pin Assignment

Block Diagram

Pullup

PLL_SEL

CLK

20 SEL1

SEL0

÷1, ÷2, ÷4, ÷8,

FB_IN

18 V_DD

17 PLL_SEL

÷16, ÷32,÷64

Pulldown

CLK

FB_IN

SEL2

V^DDO

V^DDA

SEL3

GND

QFB

Pullup

CLK

QFB

GND

PLL

V^DDO

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

Pulldown

Pullup

FB_IN

ICS8745BI-21

20-Lead SOIC

7.5mm x 12.8mm x 2.3mm package body

M Package

Pulldown

Top View

SEL0

SEL1

SEL2

SEL3

IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR

ICS8745BMI-21 REV. C APRIL 17, 2007

12 3 4 5 6 7...19

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与ICS8745BMI-21T相关器件

型号	品牌	获取价格	描述	数据表
ICS8745BY	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS8745BYI	IDT	获取价格	PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM
ICS8745BYILF	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
ICS8745BYILFT	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7
ICS8745BYLF	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS8745BYLFT	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS8745BYT	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS874S02AMI	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02AMILF	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02AMILFT	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50

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