Datasheet > ICS8745BYLF

ICS8745BYLF

更新时间： 2024-09-30 04:44:23

品牌	Logo	应用领域
矽成 - ICSI		时钟发生器逻辑集成电路驱动
页数	文件大小	规格书
15页	185K
描述
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

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ICS8745BYLF 数据手册

ICS8745B

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

GENERAL DESCRIPTION

FEATURES

The ICS8745B is a highly versatile 1:5 LVDS Clock • 5 differential LVDS outputs designed to meet

ICS

Generator and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS8745B has a fully integrated PLL

and can be configured as zero delay buffer, multi-

or exceed the requirements of ANSITIA/EIA-644

HiPerClockS™

• Selectable differential clock inputs

• CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

plier or divider, and has an output frequency range of 31.25MHz

to 700MHz. The Reference Divider, Feedback Divider and

Output Divider are each programmable, thereby allowing for

the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8.The external feedback allows the device to achieve

“zero delay” between the input clock and the output clocks.

The PLL_SEL pin can be used to bypass the PLL for system

test and debug purposes. In bypass mode, the reference clock

is routed around the PLL and into the internal output dividers.

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 30ps (maximum)

• Output skew: 35ps (maximum)

• Static phase offset: 25ps 125ps

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Lead-Free package fully RoHS compliant

BLOCK DIAGRAM

PIN ASSIGNMENT

nQ0

PLL_SEL

nQ1

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

CLK0

nCLK0

32 31 30 29 28 27 26 25

nQ2

SEL0

SEL1

CLK1

nQ3

V^DDO

nQ3

nCLK1

CLK0

PLL

nQ4

nCLK0

CLK1

CLK_SEL

ICS8745B

nQ2

GND

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

nCLK1

CLK_SEL

FB_IN

nFB_IN

nQ1

10 11 12 13 14 15 16

SEL0

SEL1

SEL2

SEL3

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

TopView

8745BY

www.icst.com/products/hiperclocks.html

REV. B DECEMBER 2, 2004

12 3 4 5 6 7...15

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与ICS8745BYLF相关器件

型号	品牌	获取价格	描述	数据表
ICS8745BYLFT	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS8745BYT	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS874S02AMI	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02AMILF	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02AMILFT	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02AMIT	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02BMI	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S02BMILF	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS874S336AG	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO24, 4.40
ICS874S336AGLFT	IDT	获取价格	PLL Based Clock Driver, 874S Series, 1 True Output(s), 0 Inverted Output(s), PDSO24, 4.40

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