Datasheet > ICS8745AYT

ICS8745AYT

更新时间： 2024-10-01 08:42:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	198K
描述
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32

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ICS8745AYT 数据手册

ICS8745

1:5 DIFFERENTIAL-TO-LVDS

ZERO DELAY CLOCK GENERATOR

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS8745 is a highly versatile 1:5 LVDS Clock • 5 differential LVDS outputs designed to meet

,&6

Generator and a member of the HiPerClockS™

family of High Performance Clock Solutions from

ICS. The ICS8745 has a fully integrated PLL and

can be configured as zero delay buffer, multi-

or exceed the requirements ofANSI TIA/EIA-644

HiPerClockS™

• Selectable differential clock inputs

• CLKx, nCLKx pairs can accept the following differential

plier or divider, and has an output frequency range of

31.25MHz to 700MHz. The Reference Divider, Feedback Di-

vider and Output Divider are each programmable, thereby

allowing for the following output-to-input frequency ratios:

8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows

the device to achieve “zero delay” between the input clock

and the output clocks. The PLL_SEL pin can be used to

bypass the PLL for system test and debug purposes. In

bypass mode, the reference clock is routed around the PLL

and into the internal output dividers.

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 25ps (maximum)

• Output skew: 35ps (maximum)

• Static phase offset: 50ps ± 150ps

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

nQ0

PLL_SEL

nQ1

÷1, ÷2, ÷4, ÷8,

÷16, ÷32, ÷64

CLK0

nCLK0

32 31 30 29 28 27 26 25

nQ2

SEL0

SEL1

CLK1

nQ3

V^DDO

nQ3

nCLK1

CLK0

PLL

nQ4

nCLK0

CLK1

CLK_SEL

ICS8745

nQ2

GND

8:1, 4:1, 2:1, 1:1,

1:2, 1:4, 1:8

nCLK1

CLK_SEL

FB_IN

nFB_IN

nQ1

10 11 12 13 14 15 16

SEL0

SEL1

SEL2

SEL3

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

8745AY

www.icst.com/products/hiperclocks.html

REV. E APRIL 14, 2003

12 3 4 5 6 7...15

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与ICS8745AYT相关器件

型号	品牌	获取价格	描述	数据表
ICS8745B	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
ICS8745BM-21	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS8745BM-21LF	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS8745BM-21LFT	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS8745BM-21T	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS8745BMI-21	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS8745BMI-21LF	IDT	获取价格	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2
ICS8745BMI-21LFT	IDT	获取价格	PLL Based Clock Driver, 8745 Series, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50
ICS8745BMI-21T	IDT	获取价格	PLL Based Clock Driver, 1 True Output(s), 0 Inverted Output(s), PDSO20, 7.50 X 12.80 MM, 2
ICS8745BY	ICSI	获取价格	1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR

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