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ICS8442 PDF预览

ICS8442

更新时间: 2024-11-05 22:55:23
品牌 Logo 应用领域
矽成 - ICSI 振荡器晶体振荡器
页数 文件大小 规格书
15页 284K
描述
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

ICS8442 数据手册

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ICS8442  
Integrated  
Circuit  
Systems, Inc.  
700MH  
Z
, CRYSTAL  
O
SCILLATOR  
-
TO-DIFFERENTIAL  
LVDS FREQUENCY  
SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8442 is a general purpose, dual output Dual differential LVDS outputs  
ICS  
Crystal-to-Differential LVDS High Frequency  
Selectable crystal oscillator interface or  
Synthesizer and a member of the HiPerClockS™  
LVCMOS/LVTTLTEST_CLK  
HiPerClockS™  
family of High Performance Clock Solutions from  
ICS. The ICS8442 has a selectable TEST_CLK  
Output frequency range: 31.25MHz to 700MHz  
Crystal input frequency range: 10MHz to 25MHz  
VCO range: 250MHz to 700MHz  
or crystal input. The TEST_CLK input accepts LVCMOS or  
LVTTL input levels and translates them to LVDS levels. The  
VCO operates at a frequency range of 250MHz to 700MHz.The  
VCO frequency is programmed in steps equal to the value of  
the input reference or crystal frequency. The VCO and output  
frequency can be programmed using the serial or parallel inter-  
face to the configuration logic.The low phase noise characteris-  
tics of the ICS8442 makes it an ideal clock source for Gigabit  
Ethernet and Sonet applications.  
Parallel or serial interface for programming counter  
and output dividers  
RMS period jitter: 2.7ps (typical)  
Cycle-to-cycle jitter: 18ps (typical)  
3.3V supply voltage  
0°C to 85°C ambient operating temperature  
“Lead-Freepackage available  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
TEST_CLK  
0
32 31 30 29 28 27 26 25  
XTAL1  
1
M5  
M6  
M7  
M8  
N0  
N1  
nc  
OSC  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL1  
XTAL2  
TEST_CLK  
XTAL_SEL  
VDDA  
ICS8442  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
PHASE DETECTOR  
÷ 1  
÷ 2  
÷ 4  
÷ 8  
MR  
0
1
GND  
VCO  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
9
10 11 12 13 14 15 16  
÷ M  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N1  
Y Package  
TopView  
8442AY  
www.icst.com/products/hiperclocks.html  
REV. C JULY 8, 2004  
1

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