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ICS84330AVT-01LF PDF预览

ICS84330AVT-01LF

更新时间: 2024-11-04 19:03:59
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
14页 157K
描述
Clock Generator, 700MHz, PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28

ICS84330AVT-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ,针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.76
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.5062 mm端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:700 MHz封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:11.5062 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

ICS84330AVT-01LF 数据手册

 浏览型号ICS84330AVT-01LF的Datasheet PDF文件第2页浏览型号ICS84330AVT-01LF的Datasheet PDF文件第3页浏览型号ICS84330AVT-01LF的Datasheet PDF文件第4页浏览型号ICS84330AVT-01LF的Datasheet PDF文件第5页浏览型号ICS84330AVT-01LF的Datasheet PDF文件第6页浏览型号ICS84330AVT-01LF的Datasheet PDF文件第7页 
PRELIMINARY  
ICS84330-01  
Integrated  
Circuit  
Systems, Incꢀ  
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V  
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
Fully integrated PLL, no external loop filter requirements  
1 differential 3.3V LVPECLoutput  
The ICS84330-01 is a general purpose, single out-  
put high frequency synthesizer and a member of  
the HiPerClockS™ family of High Performance Clock  
Solutions from ICS. The VCO operates at a fre-  
quency range of 200MHz to 700MHz. The VCO  
HiPerClockS™  
Crystal oscillator interface: 10MHz to 25MHz  
Output frequency range: 25MHz to 700MHz  
VCO range: 200MHz to 700MHz  
and output frequency can be programmed using the serial or  
parallel interfaces to the configuration logic. The output can be  
configured to divide the VCO frequency by 1, 2, 4, and 8. Out-  
put frequency steps from 250KHz to 2MHz can be achieved  
using a 16MHz crystal depending on the output divider setting.  
Parallel or serial interface for programming M and N dividers  
during power-up  
RMS Period jitter: TBD  
Cycle-to-cycle jitter: 15ps (typical)  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Pin compatible with the SY89430V  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
M0  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
nP_LOAD  
VCC  
XTAL2  
XTAL1  
nc  
M1  
2
M2  
3
M3  
4
XTAL1  
OSC  
XTAL2  
M4  
5
M5  
6
nc  
M6  
7
VCCA  
M7  
8
S_LOAD  
S_DATA  
S_CLOCK  
VCCO  
M8  
9
÷ 16  
N0  
10  
11  
12  
13  
14  
N1  
VEE  
TEST  
VCC  
FOUT  
nFOUT  
VEE  
PLL  
PHASE DETECTOR  
1
FOUT  
nFOUT  
ICS84330-01  
VCO  
÷ 2  
÷ N  
28-Lead SOIC  
0
÷ M  
7.5mm x 18.05mm x 2.25mm body package  
M Package  
Top View  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
M0:M8  
N0:N1  
25 24 23 22 21 20 19  
S_CLOCK  
26  
18  
N1  
N0  
M8  
M7  
M6  
M5  
M4  
S_DATA  
S_LOAD  
27  
28  
1
17  
16  
15  
14  
13  
12  
ICS84330-01  
28-Lead PLCC  
V Package  
VCCA  
nc  
2
11.6mm x 11.4mm x 4.1mm  
Top View  
nc  
3
4
XTAL1  
5
6
7
8
9 10 11  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
84330AV-01  
www.icst.com/products/hiperclocks.html  
REV. A FEBRUARY 14, 2003  
1

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