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ICS84324DMT

更新时间: 2024-11-04 08:13:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
13页 783K
描述
Clock Generator, 125MHz, PDSO24, 0.300 INCH, MS-013, MO-119, SOIC-24

ICS84324DMT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.87
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:15.525 mm端子数量:24
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:125 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):225
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER

ICS84324DMT 数据手册

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PRELIMINARY  
ICS84324  
Integrated  
Circuit  
Systems, Incꢀ  
CRYSTAL-TO-3.3V LVPECL  
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS84324 is a Crystal-to-3.3V LVPECL Fre- 6 differential 3.3V LVPECLoutputs  
,&6  
quency Synthesizer with Fanout Buffer and a mem-  
ber of the HiPerClockS™ family of High Performance  
Clock Solutions from ICS. Output frequency can  
be programmed using the feedback and output fre-  
Crystal oscillator interface  
HiPerClockS™  
Output frequency range: 53.125MHz to 125MHz  
Crystal input frequency: 25MHz  
Cycle-to-cycle jitter: 25ps (typical)  
quency select pins. The low phase noise characteristics of the  
ICS84324 make it an ideal clock source for Fibre Channel 1 and  
Gigabit Ethernet applications.  
RMS phase jitter at 106.25MHz, using a 25MHz crystal  
(637KHz to 10Mhz): 4.15ps  
FUNCTION TABLE  
Typical Phase noise at 106.25MHz  
Offset  
Noise Power  
Inputs  
Output Frequency  
F_OUT  
100Hz ..................-80dBc/Hz  
1KHz ................ -105dBc/Hz  
10KHz ................ -125dBc/Hz  
100KHz ................ -125dBc/Hz  
MR F_SEL1 F_SEL0  
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
LOW  
53.125MHz  
106.25MHz  
62.5MHz  
3.3V supply voltage  
0°C to 70°C ambient operating temperature  
Industrial termperature information available upon request  
125MHz  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
Q1  
nQ1  
Q2  
nQ2  
Q3  
nQ3  
Q4  
1
2
3
4
24  
23  
22  
VCC  
F_SEL0  
F_SEL1  
MR  
XTAL1  
XTAL2  
VEE  
XTAL1  
OSC  
XTAL2  
6
Q0:Q5  
21  
20  
19  
18  
17  
16  
15  
14  
13  
0
/
Output  
Divider  
5
6
7
6
/
nQ0:nQ5  
1
PLL  
8
9
10  
11  
12  
VCCA  
VCC  
PLL_SEL  
VEE  
nQ4  
Q5  
nQ5  
Feedback  
Divider  
VCC  
ICS84324  
24-Lead, 300-MIL SOIC  
7.5mm x 15.33mm x 2.3mm body package  
M Package  
Top View  
F_SEL1  
MR  
PLL_SEL  
F_SEL0  
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
84324DM  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 30, 2003  
1

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