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ICS84021AY PDF预览

ICS84021AY

更新时间: 2024-11-13 22:36:19
品牌 Logo 应用领域
矽成 - ICSI 晶体外围集成电路时钟
页数 文件大小 规格书
14页 253K
描述
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER

ICS84021AY 数据手册

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ICS84021  
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL  
FREQUENCY SYNTHESIZER  
Integrated  
Circuit  
Systems, Inc.  
GENERAL DESCRIPTION  
FEATURES  
2 LVCMOS/LVTTL outputs  
The ICS84021 is a general purpose, Crystal-to-  
ICS  
LVCMOS/LVTTL High Frequency Synthesizer  
and a member of the HiPerClockSfamily of  
High Performance Clock Solutions from ICS.The  
ICS84021 has a selectable TEST_CLK or crys-  
Selectable crystal oscillator interface  
or LVCMOS/LVTTL TEST_CLK  
HiPerClockS™  
Output frequency range: 103.3MHz to 260MHz  
Crystal input frequency range: 14MHz to 40MHz  
VCO range: 620MHz to 780MHz  
tal input.The VCO operates at a frequency range of 620MHz  
to 780MHz. The VCO frequency is programmed in steps  
equal to the value of the input reference or crystal frequency.  
The VCO and output frequency can be programmed using  
the serial or parallel interface to the configuration logic. The  
low phase noise characteristics of the ICS84021 make it an  
ideal clock source for Gigabit Ethernet, SONET, Fibre Chan-  
nel 1 and 2, and Infiniband applications.  
Parallel or serial interface for programming counter  
and output dividers  
RMS period jitter: 4.3ps (typical) (N ÷ 4, VDDO = 3.3V ꢀ5)  
RMS phase jitter at 1ꢀꢀ.ꢀ2MHz, using a 38.88MHz crystal  
(12KHz to 20MHz): 2.88ps (typical)  
Phase noise: 1ꢀꢀ.ꢀ2MHz  
Offset  
Noise Power  
100Hz ................. -93.7 dBc/Hz  
1KHz ............... -111.3 dBc/Hz  
10KHz ............... -120.4 dBc/Hz  
100KHz ............... -12ꢀ.1 dBc/Hz  
Full 3.3V or mixed 3.3V core/2.ꢀV or 1.8V supply voltage  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
OE0  
OE1  
VCO_SEL  
XTAL_SEL  
32 31 30 29 28 27 26 2ꢀ  
Mꢀ  
M6  
M7  
M8  
N0  
N1  
nc  
1
2
3
4
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL2  
TEST_CLK  
0
TEST_CLK  
XTAL_SEL  
VDDA  
XTAL1  
1
OSC  
ICS84021  
XTAL2  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
GND  
PHASE DETECTOR  
9
10 11 12 13 14 1ꢀ 16  
÷3  
÷4  
÷ꢀ  
÷6  
0
1
MR  
VCO  
Q0  
Q1  
÷ M  
32-Lead LQFP  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
7mm x 7mm x 1.4mm package body  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
Y Package  
Top View  
M0:M8  
N0:N1  
84021AY  
www.icst.com/products/hiperclocks.html  
REV. A NOVEMBER 7, 2003  
1

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