Datasheet > ICS613MLF

ICS613MLF

更新时间： 2024-11-07 11:14:31

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
6页	133K
描述
LOW PHASE NOISE CLOCK MULTIPLIER

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ICS613MLF 数据手册

ICS613

LOW PHASE NOISE CLOCK MULTIPLIER

Description

Features

The ICS613 is a low cost, low phase noise, high

• Packaged in 16 pin SOIC

performance clock synthesizer for any applications that

require low phase noise and low jitter. It is ICS’ lowest

phase noise multiplier. Using ICS’ patented analog and

digital Phase Locked Loop (PLL) techniques, the chip

can accept a 25MHz crystal or clock input, and

produces output clocks up to 157.5 MHz.

• Available in Pb (lead) free package

• Uses a fundamental 25MHz crystal or clock

• Operating voltage of 3.3 V

• Separate output voltage supplies which can run at

2.5 V or 3.3 V

The chip has separate power supplies for the clock

outputs, allowing each output to be run at different

voltages. It also allows the core of the chip to operate at

3.3V, while the output clocks run at either 2.5V or 3.3V.

• Output clocks up to 157.5 MHz

• Low phase noise: -110 dBc/Hz at 10 kHz

• Low jitter of 36 ps (one sigma)

• Advanced, low power, sub-micron CMOS process

Block Diagram

VDDO1

VDD

Phase

Comparator,

X1/ICLK

VCO

CLK1

CLK2

Charge Pump,

and Loop Filter

Reference

Divider

Crystal

Oscillator

Output

Divider

Crystal or

clock input

VCO

Divider

Capacitors must be used

with a crystal input

GND

VDDO2

S2:SO

MDS 613 C

Revision 111204

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5 6

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