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ICS501GLF PDF预览

ICS501GLF

更新时间: 2024-11-09 13:08:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
9页 101K
描述
Clock Generator, 160MHz, CMOS, PDSO8, 3 MM, GREEN, MSOP-8

ICS501GLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:MSOP
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
其他特性:ALSO OPERATES AT 5V SUPPLYJESD-30 代码:S-PDSO-G8
JESD-609代码:e3长度:3 mm
湿度敏感等级:3端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:160 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3/5 V
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Clock Generators
最大供电电压:5.25 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

ICS501GLF 数据手册

 浏览型号ICS501GLF的Datasheet PDF文件第2页浏览型号ICS501GLF的Datasheet PDF文件第3页浏览型号ICS501GLF的Datasheet PDF文件第4页浏览型号ICS501GLF的Datasheet PDF文件第5页浏览型号ICS501GLF的Datasheet PDF文件第6页浏览型号ICS501GLF的Datasheet PDF文件第7页 
DATASHEET  
LOCO™ PLL CLOCK MULTIPLIER  
ICS501  
Description  
Features  
TM  
The ICS501 LOCO is the most cost effective way to  
Packaged as 8-pin SOIC, MSOP, or die  
generate a high-quality, high-frequency clock output from a  
lower frequency crystal or clock input. The name LOCO  
stands for Low Cost Oscillator, as it is designed to replace  
crystal oscillators in most electronic systems. Using  
Phase-Locked Loop (PLL) techniques, the device uses a  
standard fundamental mode, inexpensive crystal to  
produce output clocks up to 160 MHz.  
RoHS 5 (green) or RoHS 6 (green and lead free)  
compliant packaging  
IDT’s lowest cost PLL clock  
Zero ppm multiplication error  
Input crystal frequency of 5 - 27 MHz  
Input clock frequency of 2 - 50 MHz  
Output clock frequencies up to 160 MHz  
Extremely low jitter of 25 ps (one sigma)  
Compatible with all popular CPUs  
Duty cycle of 45/55 up to 160 MHz  
Nine selectable frequencies  
Stored in the chip’s ROM is the ability to generate nine  
different multiplication factors, allowing one chip to output  
many common frequencies (see table on page 2).  
The device also has an output enable pin which tri-states  
the clock output when the OE pin is taken low.  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined or guaranteed. For  
applications which require defined input to output skew, use  
the ICS570B.  
Operating voltage of 3.3 V or 5.0 V  
Tri-state output for board level testing  
25 mA drive capability at TTL levels  
Ideal for oscillator replacement  
Industrial temperature version available  
Advanced, low-power CMOS process  
Block Diagram  
VDD  
2
S1:0  
PLL Clock  
Multiplier  
Circuitry  
and ROM  
X1/ICLK  
CLK  
Crystal or  
Clock input  
Crystal  
Oscillator  
X2  
Optional crystal capacitors  
OE  
GND  
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER  
1
ICS501  
REV R 051310  

ICS501GLF 替代型号

型号 品牌 替代类型 描述 数据表
ICS501G IDT

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Clock Generator, 160MHz, CMOS, PDSO8, 3 MM, MSOP-8
ICS501GI IDT

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Clock Generator, 140MHz, CMOS, PDSO8, 3 MM, MSOP-8

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