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ICS501A

更新时间: 2024-11-14 05:39:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
6页 172K
描述
LOCO™ PLL CLOCK MULTIPLIER

ICS501A 数据手册

 浏览型号ICS501A的Datasheet PDF文件第2页浏览型号ICS501A的Datasheet PDF文件第3页浏览型号ICS501A的Datasheet PDF文件第4页浏览型号ICS501A的Datasheet PDF文件第5页浏览型号ICS501A的Datasheet PDF文件第6页 
DATASHEET  
LOCO™ PLL CLOCK MULTIPLIER  
ICS501A  
Description  
Features  
TM  
The ICS501A LOCO is the most cost effective way to  
Packaged as 8-pin SOIC (Pb-free) or die  
IDT’s lowest cost PLL clock  
generate a high quality, high frequency clock output  
from a lower frequency crystal or clock input. The name  
LOCO stands for Low Cost Oscillator, as it is designed  
to replace crystal oscillators in most electronic  
systems. Using Phase-Locked Loop (PLL) techniques,  
the device uses a standard fundamental mode,  
inexpensive crystal to produce output clocks up to 200  
MHz.  
Zero ppm multiplication error  
Input crystal frequency of up to 27 MHz  
Input clock frequency of up to 50 MHz  
Output clock frequencies up to 200 MHz  
Extremely low jitter of 25 ps (one sigma)  
Compatible with all popular CPUs  
Duty cycle of 45/55 up to 200 MHz  
Nine selectable frequencies  
Stored in the chip’s ROM is the ability to generate nine  
different multiplication factors, allowing one chip to  
output many common frequencies (see table on page  
2).  
Operating voltage of 3.3 V  
The device also has an output enable pin which  
Tri-state output for board level testing  
25 mA drive capability at TTL levels  
Ideal for oscillator replacement  
tri-states the clock output when the OE pin is taken low.  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined or guaranteed.  
For applications which require defined input to output  
skew, use the ICS570B.  
Optimized for output frequencies of up to 200 MHz  
(166 MHz maximum for industrial temperature  
version)  
Industrial temperature version available  
Advanced, low power CMOS process  
Block Diagram  
VDD  
2
S1:0  
PLL Clock  
Multiplier  
Circuitry  
and ROM  
X1/ICLK  
CLK  
Crystal or  
Clock input  
Crystal  
Oscillator  
X2  
Optional crystal capacitors  
OE  
GND  
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER  
1
ICS501A  
REV F 051310  

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