Datasheet > IC41LV16105-60K

IC41LV16105-60K

更新时间： 2024-02-22 20:19:25

品牌	Logo	应用领域
矽成 - ICSI		动态存储器光电二极管内存集成电路
页数	文件大小	规格书
18页	188K
描述
Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO42,

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技术参数
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IC41LV16105-60K 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	SOJ, SOJ42,.44	Reach Compliance Code：	unknown
风险等级：	5.83	Is Samacsys：	N
最长访问时间：	60 ns	I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J42	JESD-609代码：	e0
内存密度：	16777216 bit	内存集成电路类型：	FAST PAGE DRAM
内存宽度：	16	端子数量：	42
字数：	1048576 words	字数代码：	1000000
最高工作温度：	70 °C	最低工作温度：
组织：	1MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOJ
封装等效代码：	SOJ42,.44	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	1024
自我刷新：	NO	最大待机电流：	0.0005 A
子类别：	DRAMs	最大压摆率：	0.145 mA
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

IC41LV16105-60K 数据手册

IC41C16105

IC41LV16105

ꢀunctional Description

Write Cycle

The IC41C16105 and IC41LV16105 is a CMOS DRAM

optimized for high-speed bandwidth, low power

applications. During READ or WRITE cycles, each bit is

uniquely addressed through the 10 address bits. These

are entered ten bits (A0-A9) at a time. The row address is

latched by the Row Address Strobe (RAS). The column

address is latched by the Column Address Strobe (CAS).

RAS is used to latch the first ten bits and CAS is used the

latter ten bits.

A write cycle is initiated by the falling edge of CAS and WE,

whichever occurs last. The input data must be valid at or

before the falling edge of CAS or WE, whichever occurs

last.

Refresh Cycle

To retain data, 1,024 refresh cycles are required in each

16 ms period. There are two ways to refresh the memory.

The IC41C16105 and IS41LV16105 has twoCAS controls,

LCAS and UCAS. The LCAS and UCAS inputs internally

generates a CAS signal functioning in an identical manner

to the single CAS input on the other 1M x 16 DRAMs. The

key difference is that each CAS controls its corresponding

I/O tristate logic (in conjunction with OE and WE and RAS).

LCAS controls I/O0 through I/O7 and UCAS controls I/O8

through I/O15.

1. By clocking each of the 1,024 row addresses (A0

through A9) with RAS at least once every 16 ms. Any

read, write, read-modify-write or RAS-only cycle re-

freshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-

RAS refresh is activated by the falling edge of RAS,

while holding CAS LOW. In CAS-before-RAS refresh

cycle, an internal 10-bit counter provides the row

addresses and the external address inputs are ignored.

The IC41C16105 and IC41LV16105 CAS function is de-

termined by the first CAS (LCAS or UCAS) transitioning

LOW and the last transitioning back HIGH. The two CAS

controls give the IC41C16105 and IC41LV16105 both

BYTE READ and BYTE WRITE cycle capabilities.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Power-On

Memory Cycle

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight initial-

ization cycles (any combination of cycles containing a

RAS signal).

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum t^RAStime has expired. A new

cycle must not be initiated until the minimum precharge

time tRP, tCP has elapsed.

During power-on, it is recommended that RAS track with

V^CCor be held at a valid VIH to avoid current surges.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time specified

by t^AR. Data Out becomes valid only when tRAC, tAA, tCAC

and tOEA are all satisfied. As a result, the access time is

dependent on the timing relationships between these

parameters.

S2-4

Integrated Circuit Solution Inc.

DR014-0A 06/07/2001

1 2 345 6 7...18

中文翻译

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与IC41LV16105-60K相关器件

型号	品牌	获取价格	描述	数据表
IC41LV16105-60KI	ETC	获取价格	1M X 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
IC41LV16105-60T	ISSI	获取价格	Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44
IC41LV16105-60T	ICSI	获取价格	Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44,
IC41LV16105-60TI	ETC	获取价格	1M X 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
IC41LV16105S	ICSI	获取价格	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
IC41LV16105S-50K	ICSI	获取价格	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
IC41LV16105S-50KI	ICSI	获取价格	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE
IC41LV16105S-50KI	ISSI	获取价格	Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO42, 0.400 INCH, SOJ-42
IC41LV16105S-50T	ISSI	获取价格	Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44
IC41LV16105S-50T	ICSI	获取价格	1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE

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