Datasheet > 存储 > DRAM> IC41C8513-60T

IC41C8513-60T

更新时间： 2024-02-09 15:09:03

品牌	Logo	应用领域
矽成 - ICSI		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
17页	231K
描述
512K x 8 bit Dynamic RAM with Fast Page Mode

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技术参数
数据手册

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IC41C8513-60T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	0.400 INCH, TSOP2-28	Reach Compliance Code：	compliant
风险等级：	5.83	Is Samacsys：	N
访问模式：	FAST PAGE	最长访问时间：	60 ns
其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G28	JESD-609代码：	e0
内存密度：	4194304 bit	内存集成电路类型：	FAST PAGE DRAM
内存宽度：	8	功能数量：	1
端口数量：	1	端子数量：	28
字数：	524288 words	字数代码：	512000
工作模式：	ASYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	TSOP28,.46
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	认证状态：	Not Qualified
刷新周期：	1024	自我刷新：	NO
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.1 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

IC41C8513-60T 数据手册

IC41C8513 and IC41LV8513

Functional Description

Refresh Cycle

The IC41C8513 and IC41LV8513 are CMOS DRAMs

optimized for high-speed bandwidth, low power

applications. During READ or WRITE cycles, each bit is

uniquely addressed through the 10 address bits. These

are entered 10 bits (A0-A9) at a time. The row address is

latched by the Row Address Strobe (RAS). The column

address is latched by the Column Address Strobe (CAS).

RAS is used to latch the first ten bits and CAS is used the

latter nine bits.

To retain data, 1,024 refresh cycles are required in each

16 ms period . There are two ways to refresh the memory:

1. By clocking each of the 1,024 row addresses (A0

through A9) with RAS at least once every 16 ms . Any

read, write, read-modify-write or RAS-only cycle re-

freshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-

RAS refresh is activated by the falling edge of RAS,

while holding CAS LOW. In CAS-before-RAS refresh

cycle, an internal 10-bit counter provides the row ad-

dresses and the external address inputs are ignored.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum t^RAStime has expired. A new

cycle must not be initiated until the minimum precharge

time t^RP, tCP has elapsed.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Power-On

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight initial-

ization cycles (any combination of cycles containing a

RAS signal).

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time specified

by t^AR. Data Out becomes valid only when tRAC, tAA, tCAC

and tOE are all satisfied. As a result, the access time is

dependent on the timing relationships between these

parameters.

During power-on, it is recommended that RAS track with

V^CCor be held at a valid VIH to avoid current surges.

Write Cycle

A write cycle is initiated by the falling edge of CAS and WE,

whichever occurs last. The input data must be valid at or

before the falling edge of CAS or WE, whichever occurs

last.

Integrated Circuit Solution Inc.

DR028-0A 09/25/2001

1 2 345 6 7...17

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与IC41C8513-60T相关器件

型号	品牌	描述	获取价格	数据表
IC41LV16100A	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41LV16100A-50K	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41LV16100A-50T	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41LV16100A-60K	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41LV16100A-60T	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41LV16100AS	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格

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