Datasheet > IBMN625805GT3B-7N

IBMN625805GT3B-7N

更新时间： 2024-11-21 15:41:11

品牌	Logo	应用领域
国际商业机器公司 - IBM		动态存储器双倍数据速率光电二极管内存集成电路
页数	文件大小	规格书
79页	1328K
描述
DDR DRAM, 32MX8, 0.75ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66

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IBMN625805GT3B-7N 技术参数

生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	TSOP2,	针数：	66
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.24	风险等级：	5.27
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	0.75 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PDSO-G66
长度：	22.22 mm	内存密度：	268435456 bit
内存集成电路类型：	DDR DRAM	内存宽度：	8
功能数量：	1	端口数量：	1
端子数量：	66	字数：	33554432 words
字数代码：	32000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32MX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1.2 mm	自我刷新：	YES
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

IBMN625805GT3B-7N 数据手册

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IBMN625404GT3B

IBMN625804GT3B

Preliminary

256Mb Double Data Rate Synchronous DRAM

Features

CAS Latency and Frequency

• DLL aligns DQ and DQS transitions with CK

transitions, also aligns QFC transitions with CK

during Read cycles

Maximum Operating Frequency (MHz)*

CAS Latency

DDR266A (7N) DDR266B (75N)

DDR200 (8N)

133

143

100

133

100

125

• Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

2.5

* Values are nominal (exact t_CKshould be used).

• Burst lengths: 2, 4, or 8

• Double data rate architecture: two data transfers

per clock cycle

• CAS Latency: 2, 2.5

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• Bidirectional data strobe (DQS) is transmitted

and received with data, to be used in capturing

data at the receiver

• 7.8µs Maximum Average Periodic Refresh

• DQS is edge-aligned with data for reads and is

center-aligned with data for writes

Interval

• Supports t

lockout feature

RAS

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• 2.5V (SSTL_2 compatible) I/O

• V = 2.5V ± 0.2V

DDQ

• V = 2.5V ± 0.2V

Description

The 256Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing

268,435,456 bits. It is internally configured as a

quad-bank DRAM.

Read and write accesses to the DDR SDRAM are

burst oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with

the registration of an Active command, which is then

followed by a Read or Write command. The address

bits registered coincident with the Active command

are used to select the bank and row to be accessed.

The address bits registered coincident with the

Read or Write command are used to select the bank

and the starting column location for the burst

access.

The 256Mb DDR SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n

prefetch architecture with an interface designed to

transfer two data words per clock cycle at the I/O

pins. A single read or write access for the 256Mb

DDR SDRAM effectively consists of a single 2n-bit

wide, one clock cycle data transfer at the internal

DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

The DDR SDRAM provides for programmable Read

or Write burst lengths of 2, 4 or 8 locations. An Auto

Precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end

of the burst access.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is a strobe transmitted by the

DDR SDRAM during Reads and by the memory

controller during Writes. DQS is edge-aligned with

data for Reads and center-aligned with data for

Writes.

As with standard SDRAMs, the pipelined, multibank

architecture of DDR SDRAMs allows for concurrent

operation, thereby providing high effective band-

width by hiding row precharge and activation time.

The 256Mb DDR SDRAM operates from a differen-

tial clock (CK and CK; the crossing of CK going high

and CK going LOW is referred to as the positive

edge of CK). Commands (address and control sig-

nals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and

output data is referenced to both edges of DQS, as

well as to both edges of CK.

An auto refresh mode is provided along with a

power-saving power-down mode. All inputs are

compatible with the JEDEC Standard for SSTL_2.

All outputs are SSTL_2, Class II compatible.

Note: The functionality described and the timing

specifications included in this data sheet are for

the DLL Enabled mode of operation.

Use is further subject to the provisions at the end of this document.

29L0011.E36997B

1/01

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与IBMN625805GT3B-7N相关器件

型号	品牌	获取价格	描述	数据表
IBMN625805GT3B-8N	IBM	获取价格	DDR DRAM, 32MX8, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
IBMPPC750CLGEQ4023	IBM	获取价格	RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA278, 21 X 21 MM, 1 MM PITCH, LEAD FREE, PLA
IBMPPC750CLGEQ4024	IBM	获取价格	RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA278, 21 X 21 MM, 1 MM PITCH, PLASTIC, MS-03
IBMPPC750CLGEQ5023	IBM	获取价格	RISC Microprocessor, 32-Bit, 500MHz, CMOS, PBGA278, 21 X 21 MM, 1 MM PITCH, LEAD FREE, PLA
IBMPPC750CLGEQ5024	IBM	获取价格	RISC Microprocessor, 32-Bit, 500MHz, CMOS, PBGA278, 21 X 21 MM, 1 MM PITCH, PLASTIC, MS-03
IBMPPC750CLGEQ6023	IBM	获取价格	暂无描述
IBMPPC750CLGEQ6024	IBM	获取价格	RISC Microprocessor, 32-Bit, 600MHz, CMOS, PBGA278, 21 X 21 MM, 1 MM PITCH, PLASTIC, MS-03
IBMPPC750CLGEQ8023	IBM	获取价格	RISC Microprocessor, 32-Bit, 800MHz, CMOS, PBGA278, 21 X 21 MM, 1 MM PITCH, LEAD FREE, PLA
IBMSGRF0100	ETC	获取价格	TRANSISTOR \| BJT \| NPN \| 4.5V V(BR)CEO \| 75MA I(C) \| SOT-353
IBMSGRF2113	IBM	获取价格	RF/Microwave Mixer, BIPolar,

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