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HY62U8200BLLSR-E-85 PDF预览

HY62U8200BLLSR-E-85

更新时间: 2024-11-02 09:45:23
品牌 Logo 应用领域
海力士 - HYNIX 静态存储器光电二极管
页数 文件大小 规格书
10页 152K
描述
Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, REVERSE, TSOP1-32

HY62U8200BLLSR-E-85 数据手册

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HY62U8200B Series  
256Kx8bit CMOS SRAM  
DESCRIPTION  
FEATURES  
The HY62U8200B is a high speed, low power and  
2M bit CMOS SRAM organized as 262,144 words  
by 8bit. The HY62U8200B uses high performance  
CMOS process technology and designed for high  
speed low power circuit technology. It is  
particularly well suited for used in high density low  
power system application. This device has a data  
retention mode that guarantees data to remain  
valid at a minimum power supply voltage of 2.0V.  
·
·
·
Fully static operation and Tri-state output  
TTL compatible inputs and outputs  
Battery backup( LL-part )  
-. 2.0V(min) data retention  
Standard pin configuration  
·
-. 32-sTSOPI-8X13.4, 32-TSOPI -8X20  
(Standard and Reversed)  
Product  
No.  
Voltage  
(V)  
Speed  
(ns)  
Operation  
Current/Icc(mA)  
Standby  
Current(uA)  
Temperature  
(°C)  
HY62U8200B  
HY62U8200B-E 2.7~3.3  
HY62U8200B-I 2.7~3.3  
2.7~3.3  
70*/85/100  
70*/85/100  
70*/85/100  
5
5
5
25  
25  
25  
0~70  
-25~85(E)  
-40~85(I)  
Note 1. Blank : Commercial, E : Extended, I : Industrial  
2. Current value is max.  
3. * measured with 30pF test load  
PIN CONNECTION  
/OE  
A10  
/CS1  
DQ8  
DQ7  
DQ6  
DQ5  
DQ4  
Vss  
DQ3  
DQ2  
DQ1  
A0  
A11  
A9  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
1
2
A3  
A4  
A5  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
16  
15  
14  
13  
12  
11  
10  
9
A2  
A8  
3
A6  
A1  
A13  
/WE  
CS2  
A15  
Vcc  
A17  
A16  
A14  
A12  
A7  
4
A0  
A7  
5
A12  
A14  
A16  
A17  
Vcc  
A15  
CS2  
/WE  
A13  
A8  
DQ1  
DQ2  
DQ3  
Vss  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
/CS1  
A10  
/OE  
6
7
8
9
8
10  
11  
12  
13  
14  
15  
16  
7
6
5
4
A6  
A1  
3
A5  
A2  
A9  
2
A4  
A3  
A11  
1
sTSOPI/TSOPI  
(Standard)  
sTSOPI/TSOPI  
(Reversed)  
PIN DESCRIPTION  
BLOCK DIAGRAM  
A0  
ROW  
DECODER  
Pin Name  
Pin Function  
I/O1  
/CS1  
Chip Select 1  
Chip Select 2  
CS2  
/WE  
Write Enable  
Output Enable  
Address Input  
Data Input/Output  
Power(2.7V~3.3V)  
Ground  
/OE  
MEMORY ARRAY  
256K x 8  
A0 ~ A17  
I/O1 ~ I/O8  
Vcc  
A17  
I/O8  
Vss  
/CS1  
/CS2  
/WE  
/OE  
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any  
responsibility for use of circuits described. No patent licenses are implied.  
Rev.02 /Jun. 2000  
Hyundai Semiconductor  

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