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HY5V56BLF-H PDF预览

HY5V56BLF-H

更新时间: 2022-12-01 20:27:03
品牌 Logo 应用领域
海力士 - HYNIX 动态存储器
页数 文件大小 规格书
13页 294K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 13.50 X 8 MM, 0.80 MM PITCH, FBGA-54

HY5V56BLF-H 数据手册

 浏览型号HY5V56BLF-H的Datasheet PDF文件第5页浏览型号HY5V56BLF-H的Datasheet PDF文件第6页浏览型号HY5V56BLF-H的Datasheet PDF文件第7页浏览型号HY5V56BLF-H的Datasheet PDF文件第9页浏览型号HY5V56BLF-H的Datasheet PDF文件第10页浏览型号HY5V56BLF-H的Datasheet PDF文件第11页 
HY5V56B(L/S)F  
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)  
-H  
-8  
-P  
-S  
Parameter  
Symbol  
Unit  
Note  
Min  
7.5  
10  
2.5  
2.5  
-
Max  
Min  
8
Max  
Min  
10  
10  
3
Max  
Min  
10  
12  
3
Max  
CAS Latency = 3  
CAS Latency = 2  
tCK3  
tCK2  
tCHW  
tCLW  
tAC3  
tAC2  
tOH  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
System Clock Cycle  
1000  
1000  
1000  
1000  
Time  
10  
3
Clock High Pulse Width  
Clock Low Pulse Width  
-
-
-
-
-
-
-
1
1
-
3
3
3
CAS Latency = 3  
CAS Latency = 2  
5.4  
-
6
6
-
-
6
6
-
-
6
6
-
Access Time From  
Clock  
2
-
6
-
-
-
Data-Out Hold Time  
Data-Input Setup Time  
Data-Input Hold Time  
Address Setup Time  
Address Hold Time  
CKE Setup Time  
2.5  
2
-
-
2.5  
2
2.5  
2
2.5  
2
tDS  
-
-
-
1
1
1
1
1
1
1
1
tDH  
0.8  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
1
-
1
-
1
-
1
-
tAS  
-
2
-
2
-
2
-
tAH  
-
1
-
1
-
1
-
tCKS  
tCKH  
tCS  
-
2
-
2
-
2
-
CKE Hold Time  
-
1
-
1
-
1
-
Command Setup Time  
Command Hold Time  
-
2
-
2
-
2
-
tCH  
-
1
-
1
-
1
-
CLK to Data Output in Low-Z Time  
tOLZ  
tOHZ3  
tOHZ2  
-
1
-
1
-
1
-
CAS Latency = 3  
2.0  
2.0  
5.4  
6
2.0  
2.0  
6
6
2.0  
2.0  
6
6
2.0  
2.0  
6
6
CLK to Data Output in  
High-Z Time  
CAS Latency = 2  
Note :  
1.Assume tR / tF (input rise and fall time ) is 1ns  
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter  
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v  
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter  
Rev. 0.1/Oct. 02  
9

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