HY5V56B(L/S)F Series
4 Banks x 4M x 16bits Synchronous DRAM
DESCRIPTION
Preliminary
The HY5V56B(L)F is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which
require low power consumption and industrial temperature range. HY5V56B(L)F is organized as 4banks of
4,194,304x16
HY5V56B(L)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
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Single 3.3±0.3V power supply
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Auto refresh and self refresh
All device balls are compatible with LVTTL interface
54Ball FBGA (13.5mm x 8.0mm)
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
All inputs and outputs referenced to positive edge of
system clock
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Data mask function by UDQM or LDQM
Internal four banks operation
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Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY5V56BF-H
HY5V56BF-8
133MHz
125MHz
100MHz
100MHz
133MHz
125MHz
100MHz
100MHz
Normal
HY5V56BF-P
HY5V56BF-S
4Banks x 4Mbits
x16
LVTTL
54ball FBGA
HY5V56B(L)F-H
HY5V56B(L)F-8
HY5V56B(L)F-P
HY5V56B(L)F-S
Low power
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1/Oct. 02
2