Datasheet > HY5V56BLF-H

HY5V56BLF-H

更新时间： 2022-12-01 20:27:03

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
13页	294K
描述
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PBGA54, 13.50 X 8 MM, 0.80 MM PITCH, FBGA-54

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HY5V56BLF-H 数据手册

HY5V56B(L/S)F

BALL DESCRIPTION

BALL OUT

SYMBOL

TYPE

DESCRIPTION

CLK

INPUT

Clock : The system clock input. All other inputs are registered

to the SDRAM on the rising edge of CLK

CKE

INPUT

Clock Enable : Controls internal clock signal and when deacti-

vated, the SDRAM will be one of the states among power

down, suspend or self refresh

INPUT

Chip Select : Enables or disables all inputs except CLK, CKE,

UDQM and LDQM

G7,G8

BA0, BA1

Bank Address : Selects bank to be activated during RAS activ-

ity

Selects bank to be read/written during CAS activity

H7, H8, J8, J7, A0 ~ A12

J3, J2, H3, H2,

H1, G3, H9, G2,

INPUT

Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8

Auto-precharge flag : A10

F8, F7, F9

RAS, CAS, INPUT

Command Inputs : RAS, CAS and WE define the operation

Refer function truth table for details

F1, E8

UDQM,

LDQM

INPUT

I/O

Data Mask:Controls output buffers in read mode and masks

input data in write mode

A8, B9, B8, C9, DQ0 ~

C8, D9, D8, E9, DQ15

E1, D2, D1, C2,

Data Input/Output:Multiplexed data input/output ball

C1, B2, B1, A2

A9, E7, J9, A1, VDD/VSS

SUPPLY

Power supply for internal circuits

Power supply for output buffers

No connection

E3, J1

A7, B3, C7, D3, VDDQ/

A3, B7, C3, D7 VSSQ

E2, G1

1 234 5 6 7...13

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