Datasheet > HY57V641620HGT-5

HY57V641620HGT-5

更新时间： 2024-02-03 01:48:31

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
12页	88K
描述
4 Banks x 1M x 16Bit Synchronous DRAM

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中文翻译

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数据手册

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HY57V641620HGT-5 数据手册

HY57V641620HG

4 Banks x 1M x 16Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.

HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated

by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of

read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst

read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Auto refresh and self refresh

•

Single 3.3±0 . 3 V p o w e r s u p p l y ^{N o t e )}

4096 refresh cycles / 64ms

•

All device pins are compatible with LVTTL interface

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

J E D E C s t a n d a r d 4 0 0 m i l 5 4 p i n T S O P - I I w i t h 0 . 8 m m

of pin pitch

•

All inputs and outputs referenced to positive edge of

system clock

•

P r o g r a m m a b l e C A S Latency ; 2, 3 Clocks

•

D a t a m a s k f u n c t i o n b y U D Q M o r L D Q M

Internal four banks operation

OR D E R IN G INF ORMAT ION

Par t No.

C l ock Fr equency

Po we r

Or gani zat i on

I nt erf ace

Package

H Y 5 7 V 6 4 1 6 2 0 H G T - 5 / 5 5 / 6 / 7

H Y 5 7 V 6 4 1 6 2 0 H G T - K

H Y 5 7 V 6 4 1 6 2 0 H G T - H

H Y 5 7 V 6 4 1 6 2 0 H G T - 8

2 0 0 / 1 8 3 / 1 6 6 / 1 4 3 M H z

1 3 3 M H z

N o r m a l

1 2 5 M H z

H Y 5 7 V 6 4 1 6 2 0 H G T - P

H Y 5 7 V 6 4 1 6 2 0 H G T - S

H Y 5 7 V 6 4 1 6 2 0 H G L T - 5 / 5 5 / 6 / 7

H Y 5 7 V 6 4 1 6 2 0 H G L T - K

H Y 5 7 V 6 4 1 6 2 0 H G L T - H

H Y 5 7 V 6 4 1 6 2 0 H G L T - 8

H Y 5 7 V 6 4 1 6 2 0 H G L T - P

H Y 5 7 V 6 4 1 6 2 0 H G L T - S

1 0 0 M H z

4 B a n k s x 1 M b i t s

x 1 6

L V T T L

400mil 54pin TSOP II

2 0 0 / 1 8 3 / 1 6 6 / 1 4 3 M H z

1 3 3 M H z

L o w p o w e r

1 2 5 M H z

1 0 0 M H z

Not e : VDD( M in) of HY5 7 V6 4 1 6 2 0 HG( L) T- 5 /55/ 6 i s 3. 135V

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0. 5/ Jun. 01

12 3 4 5 6 7...12

中文翻译

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与HY57V641620HGT-5相关器件

型号	品牌	获取价格	描述	数据表
HY57V641620HGT-55	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-55I	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-5I	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-6	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-6I	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-7	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-7I	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-8	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-8I	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM
HY57V641620HGT-H	HYNIX	获取价格	4 Banks x 1M x 16Bit Synchronous DRAM

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