HY57V56820CT-K

更新时间： 2024-11-30 04:58:03

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
12页	83K
描述
4 Banks x 8M x 8Bit Synchronous DRAM

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中文翻译

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HY57V56820CT-K 数据手册

HY57V56820C(L)T

4 Banks x 8M x 8Bit Synchronous DRAM

DESCRIPTION

The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large

memory density and high bandwidth. The HY57V56820C is organized as 4banks of 8,388,608x8.

The HY57V56820C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or

write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

8192 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V56820CT-6

HY57V56820CT-K

HY57V56820CT-H

HY57V56820CT-8

HY57V56820CT-P

HY57V56820CT-S

HY57V56820CLT-6

HY57V56820CLT-K

HY57V56820CLT-H

HY57V56820CLT-8

HY57V56820CLT-P

HY57V56820CLT-S

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 8Mbits x8

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0.4 / July 2003

12 3 4 5 6 7...12

中文翻译

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与HY57V56820CT-K相关器件

型号	品牌	获取价格	描述	数据表
HY57V56820CT-P	HYNIX	获取价格	4 Banks x 8M x 8Bit Synchronous DRAM
HY57V56820CTP-6	HYNIX	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE
HY57V56820CTP-K	HYNIX	获取价格	暂无描述
HY57V56820CTP-P	HYNIX	获取价格	Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE,
HY57V56820CTP-S	HYNIX	获取价格	Synchronous DRAM, 32MX8, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE,
HY57V56820CT-S	HYNIX	获取价格	4 Banks x 8M x 8Bit Synchronous DRAM
HY57V56820FLTP-H	HYNIX	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.875 X 0.400 INCH, 0.80 MM PITCH, LEAD FREE
HY57V56820FT-6	HYNIX	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.875 X 0.400 INCH, 0.80 MM PITCH, TSOP2-54
HY57V56820FTP-6	HYNIX	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.875 X 0.400 INCH, 0.80 MM PITCH, LEAD FREE
HY57V56820FTP-H	HYNIX	获取价格	Synchronous DRAM, 32MX8, 5.4ns, CMOS, PDSO54, 0.875 X 0.400 INCH, 0.80 MM PITCH, LEAD FREE

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