Datasheet > HY57V561620AT-10

HY57V561620AT-10

更新时间： 2024-11-23 23:57:11

品牌	Logo	应用领域
其他 - ETC		内存集成电路光电二极管动态存储器时钟
页数	文件大小	规格书
12页	155K
描述
x16 SDRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

HY57V561620AT-10 数据手册

HY57V561620AT

4 Banks x 4M x 16Bit Synchronous DRAM

DESCRIPTION

The Hyundai HY57V561620A is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V561620A is organized as 4banks of 4,194,304x16.

HY57V561620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or

write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

8192 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by UDQM, LDQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V561620AT-6

HY57V561620AT-H

HY57V561620AT-8

HY57V561620AT-P

HY57V561620AT-S

HY57V561620AT-10

HY57V561620ALT-6

HY57V561620ALT-H

HY57V561620ALT-8

HY57V561620ALT-P

HY57V561620ALT-S

HY57V561620ALT-10

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits x16

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 0.1/Dec.99

12 3 4 5 6 7...12

中文翻译

下载PDF

与HY57V561620AT-10相关器件

型号	品牌	获取价格	描述	数据表
HY57V561620AT-6	ETC	获取价格	x16 SDRAM
HY57V561620AT-8	ETC	获取价格	x16 SDRAM
HY57V561620AT-H	ETC	获取价格	x16 SDRAM
HY57V561620AT-P	ETC	获取价格	x16 SDRAM
HY57V561620AT-S	ETC	获取价格	x16 SDRAM
HY57V561620B	HYNIX	获取价格	4 Banks x 4M x 16Bit Synchronous DRAM
HY57V561620BLT	ETC	获取价格	16Mx16\|3.3V\|8K\|K\|SDR SDRAM - 256M
HY57V561620BLT-6	HYNIX	获取价格	Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
HY57V561620BLT-6I	HYNIX	获取价格	4 Banks x 4M x 16Bit Synchronous DRAM
HY57V561620BLT-8	HYNIX	获取价格	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

与HY57V561620AT-10相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V561620AT-10

HY57V561620AT-10 数据手册

与HY57V561620AT-10相关器件

与HY57V561620AT-10相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HY57V561620AT-10

HY57V561620AT-10 数据手册

与HY57V561620AT-10相关器件

与HY57V561620AT-10相关文章

您还可以找

您在本页遇到什么问题？