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HY514404AJ50 PDF预览

HY514404AJ50

更新时间: 2024-01-11 02:27:51
品牌 Logo 应用领域
其他 - ETC 动态存储器
页数 文件大小 规格书
8页 114K
描述
x4 EDO Page Mode DRAM

HY514404AJ50 数据手册

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HY514404A  
1Mx4, Extended Data Out mode  
DESCRIPTION  
This family is a 4M bit dynamic RAM organized 1,048,576 x 4-bit configuration with Extended Data Out mode CMOS  
DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The circuit and process  
design allow this device to achieve high performance and low power dissipation. Optional features are access time(50, 60  
or 70ns) and package type(SOJ, TSOP-II) and power consumption (Normal or Low power with self refresh). Hyundai’s  
advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and  
high reliability.  
FEATURES  
Ÿ Extended data out operation  
Ÿ Read-modify-write Capability  
Ÿ TTL compatible inputs and outputs  
Ÿ /CAS-before-/RAS, /RAS-only, Hidden and  
Self refresh capability  
Ÿ JEDEC standard pinout  
Ÿ 20/26-pin SOJ (300mil)  
20/26-pin TSOP-II (300mil)  
Ÿ Single power supply of 5V ± 10%  
Ÿ Early Write or output enable controlled write  
Ÿ Fast access time and cycle time  
Ÿ Max. Active power dissipation  
Speed  
50  
Power  
605mW  
495mW  
412mW  
Speed  
50  
tRAC  
50ns  
60ns  
70ns  
tCAC  
13ns  
15ns  
20ns  
tHPC  
20ns  
25ns  
30ns  
60  
60  
70  
70  
Ÿ Refresh cycle  
Part number  
Refresh  
1K  
Normal  
SL-part  
HY514404A  
16ms  
128ms  
ORDERING INFORMATION  
Part Name  
HY514404AJ  
Refresh  
Power  
L-part  
L-part  
Package  
1K  
1K  
1K  
1K  
20/26Pin SOJ  
HY514404ALJ  
HY514404AT  
20/26Pin SOJ  
20/26Pin TSOP-II  
20/26Pin TSOP-II  
HY514404ALT  
*SL : Low power with self refresh  
This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of  
circuits described. No patent licences are implied  
Hyundai Semiconductor  
Rev.10 / Jan.97  
1
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