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HV9808PJ-GM903 PDF预览

HV9808PJ-GM903

更新时间: 2024-02-18 22:47:57
品牌 Logo 应用领域
超科 - SUPERTEX 驱动接口集成电路
页数 文件大小 规格书
7页 481K
描述
32-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs

HV9808PJ-GM903 技术参数

生命周期:Unknown包装说明:,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.68
Is Samacsys:N接口集成电路类型:EL DISPLAY DRIVER
Base Number Matches:1

HV9808PJ-GM903 数据手册

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Supertex inc.  
HV9808  
32-Channel Serial to Parallel Converter  
With High Voltage Push-Pull Outputs  
Features  
General Description  
Processed with HVCMOS® technology  
Output voltages up to 80V  
The HV9808 is a low voltage serial to high voltage parallel  
converters with push-pull outputs. This device has been designed  
for use as a driver for AC-electroluminescent displays.It can also  
be used in any application requiring multiple output, high voltage  
current sourcing and sinking capabilities such as driving plasma  
panels, vacuum fluorescent, or large matrix LCD displays. The  
inputs are fully CMOS compatible.  
Low power level shifting  
Shift register speed 8.0MHz  
Latched data outputs  
5.0V CMOS compatible inputs  
Forward and reverse shifting options  
Diode to VPP allows efficient power recovery  
This device consists of a 32-bit shift register, 32 latches, and  
control logic to perform the polarity select and blanking of the  
outputs. HVOUT1 is connected to the first stage of the shift register  
through the polarity and blanking logic. Data is shifted through  
the shift register on the logic low to high transition of the clock.  
The HV9808 shifts data in the counter-clockwise direction when  
viewed from the top of the package. A data output buffer is  
provided for cascading devices.This output reflects the current  
status of the last bit of the shift register (HVOUT32). Operation  
of the shift register is not affected by the LE (latch enable), BL  
(blanking), or the POL (polarity) in-puts. Transfer of data from the  
shift register to the latch occurs when the LE (latch enable) input  
is high. The data in the latch is stored when LE is low.  
Block Diagram  
VPP  
POLARITY  
BLANKING  
LATCH ENABLE  
HVOUT  
1
2
DATA INPUT  
CLOCK  
Latch  
Latch  
HVOUT  
32-Bit  
Shift  
Register  
(Outputs 3 to 30  
not shown)  
HVOUT31  
Latch  
Latch  
HVOUT32  
DATA OUT  
Doc.# DSFP-HV9808  
B032714  
Supertex inc.  
www.supertex.com  

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