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HV7322 PDF预览

HV7322

更新时间: 2024-11-13 14:55:03
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
40页 1182K
描述
The HV7322 is an 8-channel, true 5-Level or pseudo 7-Level, high voltage pulser with integrated

HV7322 数据手册

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HV7322  
8-Channel 7-Level ±80V High-Voltage Pulser with T/R Switches  
Features  
Description  
• High-Voltage CMOS Technology for High  
Performance  
The HV7322 device is an 8-channel, true 5-level or  
pseudo 7-level, high-voltage pulser, with integrated T/R  
switches. HV7322 is designed for medical ultrasound  
applications. It is also fitted for NDT and other  
transducer drive applications.  
• 8-Channel, True 5-Level or Pseudo 7-Level,  
±80V, 2A, with Return-to-Zero (RTZ) to True Zero  
Voltage  
• Programmable ±0.5A, 1.0A, 1.5A and 2A Output  
Current from VPP1/VNN1  
The HV7322 device’s output has seven different volt-  
age levels: VPP0,1,2, VNN0,1,2 and GND. The output  
MOSFET transistors can provide up to ±2A of current  
at the maximum voltage of ±80V. HV7322 has channel  
RTZ for the return-to-zero feature. The three sets of  
high-voltage outputs, with ±2A of peak output current in  
B-Mode and programmable 2-bit, use the VPP1/VNN1  
voltage rails for the CW-Mode (IM<1:0> = 0), in order to  
reduce the CW-Mode power dissipations on chip.  
• Integrated Radio Frequency (RF) Blocking,  
Clamp Diode and RX Damp  
• 13Transmit/Receive (T/R) and Low Voltage  
(LV) Switches Allow Receiver Multiplexing  
• 160Auto-Bleeding Switches for RTZ True Zero  
• 220 MHz Clock Retiming Synchronization  
Capability  
The high-voltage T/R and LV analog switches (total  
13) and RX damp switch are Integrated in each chan-  
nel, while the 160RTZ switches dedicated for true  
zero voltage minimize the received noise.  
• 2.5V, 3.3V Logic Control Voltage, designed to  
work with FPGA Inputs and Outputs (I/O) directly.  
• Adjusting T/R Switch Delay, Avoid Echo  
Saturating  
The 220 MHz differential retiming clock inputs and  
built-in registers are capable of providing low jitter in  
Continuous Wave Doppler (CWD) mode, in Pulse  
Wave (PW) mode or in B-mode. The clock synchroni-  
zation realigns the logic input signals to a master clock,  
which reduces various propagation delays caused by  
FPGA inaccuracies and/or long PCB traces.  
• TX Output Frequency up to 20 MHz  
• -40 dB HD2 Second Harmonic Distortion at  
5 MHz  
• 12 mm x 12 mm x 1.20 mm 206-Lead TFBGA  
Package  
Applications  
The integrated circuit (IC) has built-in gate-driver float-  
ing voltage regulators, allowing VPP0,1,2 and VNN0,1,2  
high-voltage rails to move the voltage interdependently  
from 0 to ±80V or to 60V. Each of the pulsers has output  
voltage overshoot clamping diodes to the highest level  
of the supply pin of VPP0 or VNN0 rails respectively. The  
differential clock inputs take Differential Clock or  
LVCMOS output signals. The logic control voltages are  
designed to work with the Differential Clock or the  
LVCMOS logic families directly.  
• Medical ultrasound imaging system  
• NDT (nondestructive testing) ultrasound  
transmission pulsers  
• Piezoelectric or capacitive transducer drivers  
2017 Microchip Technology Inc.  
DS20005920A-page 1  

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