HS-80C86RH
TM
Data Sheet
August 2000
File Number 3035.2
Radiation Hardened 16-Bit CMOS
Microprocessor
Features
• Electrically Screened to SMD # 5962-95722
The Intersil HS-80C86RH high performance radiation
hardened 16-bit CMOS CPU is manufactured using a
hardened field, self aligned silicon gate CMOS process. Two
modes of operation, MINimum for small systems and
MAXimum for larger applications such as multiprocessing,
allow user configuration to achieve the highest performance
level. Industry standard operation allows use of existing
NMOS 8086 hardware and software designs.
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Performance
- Latch Up Free EPl-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
8
- Transient Upset. . . . . . . . . . . . . . . . . . . . >10 rad(Si)/s
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 500µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . 12mA/MHz (Max)
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• Pin Compatible with NMOS 8086 and Intersil 80C86
• Completely Static Design DC to 5MHz
• 1MB Direct Memory Addressing Capability
• 24 Operand Addressing Modes
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95722. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
• Bit, Byte, Word, and Block Move Operations
Ordering Information
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary or Decimal
INTERNAL
TEMP. RANGE
o
ORDERING NUMBER
5962R9572201QQC
5962R9572201QXC
5962R9572201VQC
5962R9572201VXC
HS1-80C86RH/Proto
HS9-80C86RH/Proto
MKT. NUMBER
( C)
- Multiply and Divide
HS1-80C86RH-8
HS9-80C86RH-8
HS1-80C86RH-Q
HS9-80C86RH-Q
HS1-80C86RH/Proto
HS9-80C86RH/Proto
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Bus-Hold Circuitry Eliminates Pull-up Resistors for CMOS
Designs
• Hardened Field, Self-Aligned, Junction-Isolated CMOS
Process
• Single 5V Power Supply
o
o
• Military Temperature Range . . . . . . . . . . . -35 C to 125 C
• Minimum LET for
Single Event Upset . . . . . . . . . . . . . 6MEV/mg/cm (Typ)
2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1