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HS-80C85RH

更新时间： 2024-01-13 17:53:09
品牌 Logo 应用领域
英特矽尔 - INTERSIL 微处理器
页数 文件大小 规格书
19页 162K
描述
Radiation Hardened 8-Bit CMOS Microprocessor

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中文翻译

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HS-80C85RH 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.84
Base Number Matches：1

HS-80C85RH 数据手册

 浏览型号HS-80C85RH的Datasheet PDF文件第2页浏览型号HS-80C85RH的Datasheet PDF文件第3页浏览型号HS-80C85RH的Datasheet PDF文件第4页浏览型号HS-80C85RH的Datasheet PDF文件第5页浏览型号HS-80C85RH的Datasheet PDF文件第6页浏览型号HS-80C85RH的Datasheet PDF文件第7页 
HS-80C85RH  
Radiation Hardened  
8-Bit CMOS Microprocessor  
February 1996  
Features  
Description  
• Devices QML Qualified in Accordance With  
MIL-PRF-38535  
The HS-80C85RH is an 8-bit CMOS microprocessor fabri-  
cated using the Intersil radiation hardened self-aligned junc-  
tion isolated (SAJI) silicon gate technology. Latch-up free  
operation is achieved by the use of epitaxial starting material  
to eliminate the parasitic SCR effect seen in conventional  
bulk CMOS devices.  
• Detailed Electrical and Screening Requirements are  
Contained in SMD# 5962-95824 and Intersil’ QM Plan  
• Radiation Hardened EPI-CMOS  
- Parametrics Guaranteed 1 x 105 RAD(Si)  
- Transient Upset > 1 x 108 RAD(Si)/s  
- Latch-up Free > 1 x 1012 RAD(Si)/s  
• Low Standby Current 500µA Max  
The HS-80C85RH is a functional logic emulation of the  
HMOS 8085 and its instruction set is 100% software com-  
patible with the HMOS device. The HS80C85RH is designed  
for operation with a single 5 volt power supply. Its high level  
of integration allows the construction of a radiation hardened  
microcomputer system with as few as three ICs (HS-  
80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/  
56RH RAM I/O.  
• Low Operating Current 5.0mA/MHz (X1 Input)  
• Electrically Equivalent to Sandia SA 3000  
• 100% Software Compatible with INTEL 8085  
• Operation from DC to 2MHz, Post Radiation  
• Single 5 Volt Power Supply  
• On-Chip Clock Generator and System Controller  
• Four Vectored Interrupt Inputs  
• Completely Static Design  
• Self Aligned Junction Isolated (SAJI) Process  
• Military Temperature Range -55oC to +125oC  
Pinouts  
40 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835, CDIP2-T40  
TOP VIEW  
42 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
INTERSIL OUTLINE K42.A  
TOP VIEW  
X1  
X2  
VDD  
1
2
40  
39  
38  
37  
36  
35  
34  
33  
X1  
X2  
1
2
3
4
42  
41  
40  
39  
VDD  
HOLD  
HOLD  
HLDA  
3
RESET OUT  
SOD  
RESET  
OUT  
SOD  
HLDA  
CLOCK  
OUT  
CLOCK OUT  
4
SID  
5
RESET IN  
READY  
SID  
5
6
38  
37  
RESET  
TRAP  
6
IN  
TRAP  
READY  
RST 7.5  
RST 6.5  
7
IO / M  
S1  
RST 7.5  
RST 6.5  
7
8
36  
35  
IO / M  
S1  
8
RST 5.5  
INTR  
INTA  
AD0  
9
32 RD  
31 WR  
RST 5.5  
INTR  
INTA  
AD0  
9
34  
33  
32  
31  
30  
29  
28  
27  
RD  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
15  
16  
WR  
ALE  
30  
29 S0  
ALE  
S0  
AD1  
A15  
28  
27  
26  
25  
24  
23  
AD1  
A15  
A14  
AD2  
A14  
A13  
A12  
A11  
AD2  
AD3  
AD3  
A13  
15  
16  
17  
18  
19  
20  
AD4  
A12  
A11  
AD4  
AD5  
AD6  
AD7  
GND  
NC  
NC  
17  
18  
19  
26  
25  
24  
A10  
A9  
A10  
AD5  
22 A9  
A8  
AD6  
AD7  
20  
21  
23  
22  
A8  
21  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
Spec Number 518054  
File Number 3036.2  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999  
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中文翻译

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