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HMX2000 PDF预览

HMX2000

更新时间: 2024-01-22 01:24:39
品牌 Logo 应用领域
霍尼韦尔 - HONEYWELL /
页数 文件大小 规格书
2页 161K
描述
MIXED SIGNAL SOI GATE ARRAYS

HMX2000 数据手册

 浏览型号HMX2000的Datasheet PDF文件第2页 
MIXED SIGNAL SOI GATE ARRAYS  
HMX2000  
FAMILY  
Features  
xꢀ Fabricated on Honeywell’s RICMOSTM IV Silicon  
xꢀ Linear Capacitors  
100ppm/Volt, 0.5fF/Pm2  
On Insulator (SOI) process  
-
-
0.8 Pm Process (Leff = .65 Pm)  
xꢀ Vt~0.8V  
xꢀ HMX2000 supports 5V operation  
xꢀ DMOS: NMOS AND PMOS > 20 Volts Breakdown  
xꢀ Lateral Bipolar: ǃ>20  
xꢀ TTL, CMOS, Cold Spare compatible I/O  
xꢀ 3 or 4 layer metal interconnect  
xꢀ Inductors (Metal Spiral) Q~2-5, 2-5nH  
xꢀ Body terminal fully oxide-isolated from substrate  
xꢀ Ring Oscillator Speed ~ 150 psec/stage  
xꢀ Total Dose Hardness > 1M Rad(Si)  
xꢀ No Latchup  
xꢀ Compatible with existing HX2000 digital gate arrays  
-
-
Sea-Of-Gates flow around embedded cells  
Memory, A/D, D/A and other cores available  
xꢀ Up to 275,000 gates useable  
xꢀ Typical gate toggle power 0.6 PW/MHz/gate  
xꢀ Analog on SOI provides 10dB lower substrate noise  
than bulk CMOS at 1GHz, 25dB lower at 100 MHz  
xꢀ NMOS Ft = 15 GHz  
Future enhancements  
xꢀ 3.3V digital supply and I/O  
xꢀ CrSi resistor, 2500:/square r 20%  
-
300 ppm/qC temperature coefficient  
General Description  
The HMX2000 family of arrays incorporate Mixed Signal  
capability as an extension of the available HX2000 Gate  
Array family, fabricated on Honeywell’s RICMOSTM IV  
Silicon On Insulator (SOI) process. The SOI-IV process at  
Honeywell has performance advantages over bulk silicon  
CMOS in that 25% to 35% higher speeds can be obtained  
or up to 30% lower power. The SOI substrate can support a  
6X improvement in static noise margins and significantly  
lower subthreshold leakage current.  
Each HMX2000 array design is founded on our proven  
SOI ASIC library of SSI and MSI logic elements, available  
core IP (intellectual property), integratable passives, and  
selectable I/O pads. This family is fully compatible with  
Honeywell’s range of high reliability screening, test and  
packaging options.  
Designers can choose from a wide variety of I/O types.  
Output buffer options include  
8
drive strengths,  
CMOS/TTL levels, IEEE 1149.1 boundry scan, pull-  
up/pull-down resistors, and tri-state capability. Input  
buffers can be selected for CMOS/TTL/Schmitt trigger  
levels, IEEE 1149.1 boundry scan and pull-up/pull-down  
resistors. Bi-directional buffers are also available.  
_________________________________________________________________________________________________________  
Solid State Electronics Center x 12001 State Highway 55, Plymouth, MN 55441x (800) 323-8295 x http://www.ssec.honeywell.com  

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