Datasheet > HMSD23216

HMSD23216

更新时间： 2024-11-06 11:46:35

品牌	Logo	应用领域
西迪斯 - CTS		动态存储器双倍数据速率
页数	文件大小	规格书
65页	1369K
描述
DDR2-800 SDRAM

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HMSD23216 数据手册

DDR2 SDRAM Memory

Technical Data Sheet

Description

The HMSD23216 is

high-speed CMOS Double-Data-Rate-Two (DDR2), synchronous dynamic

random-access memory (SDRAM) containing 512 Mbits in a 16-bit wide data I/Os. It is internally configured as a

quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os.

The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency,

Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT).

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.

Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with

a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to

convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the

registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write

accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for

a programmed number of locations in a programmed sequence. Operating the four memory banks in an

interleaved fashion allows random access operation to occur at a higher rate than is possible with standard

DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the

end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS#

latency, and speed grade of the device.

Features

• JEDEC Standard Compliant

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Power supplies: VDD & VDDQ = +1.8V ± 0.1V

• Supports JEDEC clock jitter specification

• Fully synchronous operation

• Fast clock rate: 333/400MHz

• Differential Clock, CK & CK#

• Bidirectional single/differential data strobe

-DQS & DQS#

• 4 internal banks for concurrent operation

• 4-bit prefetch architecture

• Internal pipeline architecture

• Precharge & active power down

• Programmable Mode & Extended Mode registers

• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5

• WRITE latency = READ latency - 1 tCK

• Burst lengths: 4 or 8

• Burst type: Sequential / Interleave

• DLL enable/disable

• Off-Chip Driver (OCD)

-Impedance Adjustment

PAGE 1

Rev. A

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