Datasheet > HMC7044

HMC7044

更新时间： 2024-11-24 14:58:03

品牌	Logo	应用领域
亚德诺 - ADI		衰减器
页数	文件大小	规格书
71页	1601K
描述
带JESD204B接口的高性能、3.2 GHz、14路输出抖动衰减器

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HMC7044 数据手册

High Performance, 3.2 GHz, 14-Output

Jitter Attenuator with JESD204B

Data Sheet

HMC7044

FEATURES

APPLICATIONS

Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at

2457.6 MHz

Noise floor: −156 dBc/Hz at 2457.6 MHz

JESD204B clock generation

Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)

Data converter clocking

Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output

Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)

from PLL2

Microwave baseband cards

Phase array reference distribution

GENERAL DESCRIPTION

Maximum CLKOUTx/

CLKOUTx

and SCLKOUTx/

SCLKOUTx

The HMC7044 is a high performance, dual-loop, integer-N

jitter attenuator capable of performing reference selection and

generation of ultralow phase noise frequencies for high speed data

converters with either parallel or serial (JESD204B type) interfaces.

The HMC7044 features two integer mode PLLs and overlapping

on-chip VCOs that are SPI-selectable with wide tuning ranges

around 2.5 GHz and 3 GHz, respectively. The device is designed to

meet the requirements of GSM and LTE base station designs and

offers a wide range of clock management and distribution

features to simplify baseband and radio card clock tree designs.

The HMC7044 provides 14 low noise and configurable outputs

to offer flexibility in interfacing with many different components

including data converters, field-programmable gate arrays

(FPGAs), and mixer local oscillators (LOs).

frequency up to 3200 MHz

JESD204B-compatible system reference (SYSREF) pulses

25 ps analog, and ½ VCO cycle digital delay independently

programmable on each of 14 clock output channels

SPI-programmable phase noise vs. power consumption

SYSREF valid interrupt to simplify JESD204B synchronization

Narrow-band, dual core VCOs

Up to 2 buffered voltage controlled oscillator (VCXO) outputs

Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes

Frequency holdover mode to maintain output frequency

Loss of signal (LOS) detection and hitless reference switching

4× GPIOs alarms/status indicators to determine the health of

the system

External VCO input to support up to 6000 MHz

On-board regulators for excellent PSRR

68-lead, 10 mm × 10 mm LFCSP_VQ

The DCLK and SYSREF clock outputs of the HMC7044 can be

configured to support signaling standards, such as CML, LVDS,

LVPECL, and LVCMOS, and different bias settings to offset

varying board insertion losses.

FUNCTIONAL BLOCK DIAGRAM

OSCIN

CPOUT1 OSCIN

CPOUT2 OSCOUT1 OSCOUT1

CLKOUT0

SCLKOUT1

CLKOUT2

SCLKOUT3

CLKIN0/RFSYNCIN

CLKIN1/FIN

PLL1

PLL2

CLKIN2/OSCOUT0

CLKIN3

CLKOUT12

SCLKOUT13

SYSREF

CONTROL

SYNC

14-CLOCK

DISTRIBUTION

SPI

CONTROL

INTERFACE

SDATA

SLEN SCLK

Figure 1.

Rev. C

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registered trademarks are the property of their respectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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与HMC7044相关器件

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HMC7044LP10BE	ADI	获取价格	High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B / JESD204C
HMC7044LP10BETR	ADI	获取价格	High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B / JESD204C
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HMC705	ADI	获取价格	6.5 GHz可编程分频器（N = 1至17）SMT
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HMC7056	HITTITE	获取价格	Up Converter
HMC7056	ADI	获取价格	Ka-Band Block Upconverter with HPA
HMC7056AG	ADI	获取价格	Ka-Band Block Upconverter with HPA
HMC705LP4	HITTITE	获取价格	6.5 GHz PROGRAMMABLE DIVIDER (N = 1 - 17)
HMC705LP4E	HITTITE	获取价格	6.5 GHz PROGRAMMABLE DIVIDER (N = 1 - 17)

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