32 Gbps Dual Channel
Advanced Linear Equalizer
Data Sheet
HMC6545
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Supports data rates from dc up to 32 Gbps
Protocol and data rate agnostic
Low latency (<170 ps)
Integrated AGC with differential sensitivity of <50 mV
Up to 20 dB programmable multiple unit interval input
equalization
Extended chromatic and polarization mode dispersion
tolerance
Programmable differential output amplitude control of up to
600 mV
Single 3.3 V supply eliminating external regulators
Wide temperature range from −40°C to +95°C
5 mm × 5 mm, 32-lead LFCSP package
HMC6545
GND 1
GND
24
23
22
21
T/2 T/2 T/2 T/2
INP0
2
OUTP0
OUTN0
GND
AGC
LPF
INN0
GND
GND
3
4
5
c0
c1
c2
cn
Σ
20 GND
SERIAL CONTROL
REGISTERS
OUTP1
INP1 6
19
AGC
T/2 T/2 T/2 T/2
7
18 OUTN1
INN1
GND 8
d0
d1
d2
dn
LPF
GND
17
Σ
APPLICATIONS
40 Gbps/100 Gbps DQPSK direct detection receivers
Short and long reach CFP2 and QSFP+ modules
CEI-28G MR and CEI-25G LR 100 GE line cards
16 Gbps and 32 Gbps Fibre Channel
Infiniband 14 Gbps FDR and 28 Gbps EDR rates
Signal conditioning for backplane and line cards
Broadband test and measurement equipment
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The HMC6545 is a low power, high performance, fully
programmable, dual-channel, asynchronous advanced linear
equalizer that operates at data rates of up to 32 Gbps. The
HMC6545 is protocol and data rate agnostic, and it can operate
on the transmit path to predistort a transmitted signal to invert
channel distortion or on the receiver path to equalize the
distorted and attenuated received signal. The HMC6545 is
effective in dealing with chromatic and polarization mode
dispersion and intersymbol interference (ISI) caused by a wide
variety of transmission media (backplane or fiber) and channel
lengths.
input of the FFE. The 9-tap FFE is programmed via 2-wire
interface to generate wide range frequency responses that are
precursor or postcursor in nature for compensating signal
impairments. After FFE tap coefficients are summed at the
summing node, the signal is received by a linear output driver.
DC offset correction circuitry is controlled either automatically
or manually via Forward Error Correction (FEC).
All high speed differential inputs and outputs of the HMC6545 are
current mode logic (CML) and terminated on chip with 50 Ω to
the positive supply, 3.3 V, and can be dc-coupled or ac-coupled.
The inputs and outputs of the HMC6545 can be operated either
differentially or single-ended. The low power, high performance,
and feature rich HMC6545 is packaged in a 5 mm × 5 mm,
32-lead LFCSP package. The device uses a single 3.3 V supply,
eliminating external regulators. The HMC6545 operates over a
−40°C to +95°C temperature range.
The HMC6545 consists of an automatic gain control (AGC);
dc offset correction circuitry; a 9-tap, 18 ps spaced feedforward
equalizer (FFE); a summing node; and a linear programmable
output driver. The input AGC linearly attenuates or amplifies
the distorted input signal to generate a constant voltage at the
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
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Tel: 781.329.4700
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www.analog.com
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