5秒后页面跳转
HI1-574AUD/883 PDF预览

HI1-574AUD/883

更新时间: 2024-02-13 12:56:13
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器微处理器
页数 文件大小 规格书
18页 202K
描述
Complete, 12-Bit A/D Converters with Microprocessor Interface

HI1-574AUD/883 技术参数

生命周期:Contact Manufacturer包装说明:DIP,
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.63
最大模拟输入电压:10 V最小模拟输入电压:-10 V
最长转换时间:25 µs转换器类型:ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码:R-CDIP-T28最大线性误差 (EL):0.0244%
标称负供电电压:-12 V模拟输入通道数量:1
位数:12功能数量:1
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C输出位码:BINARY
输出格式:PARALLEL, WORD封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
采样并保持/跟踪并保持:SAMPLE筛选级别:MIL-STD-883
标称供电电压:12 V表面贴装:NO
温度等级:MILITARY端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

HI1-574AUD/883 数据手册

 浏览型号HI1-574AUD/883的Datasheet PDF文件第12页浏览型号HI1-574AUD/883的Datasheet PDF文件第13页浏览型号HI1-574AUD/883的Datasheet PDF文件第14页浏览型号HI1-574AUD/883的Datasheet PDF文件第16页浏览型号HI1-574AUD/883的Datasheet PDF文件第17页浏览型号HI1-574AUD/883的Datasheet PDF文件第18页 
HI-574A, HI-674A, HI-774  
The 12/8 input will be tied high or low in most applications,  
though it is fully TTL/CMOS-compatible. With 12/8 high, all  
12 output lines become active simultaneously, for interface to  
a 12-bit or 16-bit data bus. The A input is ignored.  
O
CE  
CS  
t
t
t
HSR  
SSR  
With 12/8 low, the output is organized in two 8-bit bytes,  
selected one at a time by A . This allows an 8-bit data bus  
O
to be connected as shown in Figure 6. A is usually tied to  
O
t
HRR  
the least significant bit of the address bus, for storing the  
HI-X74(A) output in two consecutive memory locations.  
(With A low, the 8 MSBs only are enabled. With A high, 4  
MSBs are disabled, bits 4 through 7 are forced low, and the 4  
LSBs are enabled). This two byte format is considered “left  
justified data,” for which a decimal (or binary!) point is  
assumed to the left of byte 1:  
R/C  
O
O
SRR  
A
O
t
t
SAR  
HAR  
STS  
t
BYTE 1  
BYTE 2  
HS  
t
HD  
DATA  
VALID  
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
DB11-DB0  
HIGH IMPEDANCE  
t
t
HL  
DD  
MSB  
LSB  
Further, A may be toggled at any time without damage to  
O
See HI-774 Timing Specifications for more information.  
the converter. Break-before-make action is guaranteed  
between the two data bytes, which assures that the outputs  
strapped together in Figure 6 will never be enabled at the  
same time.  
FIGURE 5. READ CYCLE TIMING  
A read operation usually begins after the conversion is  
complete and STS is low. For earliest access to the data,  
however, the read should begin no later than (t  
before STS goes low. See Figure 5.  
+ t )  
DD  
HS  
A
ADDRESS BUS  
O
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
STS  
DB11 (MSB)  
t
HEC  
CE  
CS  
12/8  
t
SSC  
3
4
A
O
t
HSC  
t
SRC  
5
R/C  
DATA  
BUS  
6
t
HRC  
7
A
O
HI-774  
8
t
SAC  
9
t
HAC  
10  
11  
12  
13  
14  
STS  
t
C
t
DSC  
HIGH IMPEDANCE  
DB11-DB0  
DB0 (LSB) 16  
DIG.  
15  
COM.  
See HI-774 Timing Specifications for more information.  
FIGURE 4. CONVERT START TIMING  
FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS  
6-966  

与HI1-574AUD/883相关器件

型号 品牌 获取价格 描述 数据表
HI1-574AUD-2 INTERSIL

获取价格

Complete, 12-Bit A/D Converters with Microprocessor Interface
HI-1574PCI HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PCIF HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PCM HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PCMF HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PCT HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PCTF HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PSI HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PSIF HOLTIC

获取价格

3.3V Monolithic Dual Transceivers
HI-1574PSM HOLTIC

获取价格

3.3V Monolithic Dual Transceivers