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HI1-574AUD/883

更新时间： 2024-02-06 22:09:56
品牌 Logo 应用领域
英特矽尔 - INTERSIL 转换器微处理器
页数 文件大小 规格书
18页 202K
描述
Complete, 12-Bit A/D Converters with Microprocessor Interface

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中文翻译

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HI1-574AUD/883 技术参数

生命周期：Contact Manufacturer包装说明：DIP,
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.63
最大模拟输入电压：10 V最小模拟输入电压：-10 V
最长转换时间：25 µs转换器类型：ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码：R-CDIP-T28最大线性误差 (EL)：0.0244%
标称负供电电压：-12 V模拟输入通道数量：1
位数：12功能数量：1
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出位码：BINARY
输出格式：PARALLEL, WORD封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
采样并保持/跟踪并保持：SAMPLE筛选级别：MIL-STD-883
标称供电电压：12 V表面贴装：NO
温度等级：MILITARY端子形式：THROUGH-HOLE
端子位置：DUALBase Number Matches：1

HI1-574AUD/883 数据手册

 浏览型号HI1-574AUD/883的Datasheet PDF文件第9页浏览型号HI1-574AUD/883的Datasheet PDF文件第10页浏览型号HI1-574AUD/883的Datasheet PDF文件第11页浏览型号HI1-574AUD/883的Datasheet PDF文件第13页浏览型号HI1-574AUD/883的Datasheet PDF文件第14页浏览型号HI1-574AUD/883的Datasheet PDF文件第15页 
HI-574A, HI-674A, HI-774  
HI-774  
direction by up to 15 LSBs. This results in a total correction  
range of +31 to -32 LSBs. When an 8-bit conversion is per-  
The device driving the HI-774 analog input will see a nominal  
load of 5kΩ (10V range) or 10kΩ (20V range). However, the  
other end of these input resistors may change as much as  
1
formed, the input must settle to within ± / LSB at 8-bit resolu-  
2
tion (which equals ±8 LSBs at 12-bit resolution).  
±400mV with each bit decision. These input disturbances With the HI-774 a conversion can be initiated before the  
are caused by the internal DAC changing codes which input has completely settled, as long as it meets the con-  
causes a glitch on the summing junction. This creates abrupt straints of the Figure 1 window. This allows the user to start  
changes in current at the analog input causing a “kick back” conversion up to 4.8µs earlier than with a typical analog to  
glitch from the input. Because the algorithm starts with the digital converter. A typical successive approximation type  
MSB, the first glitches will be the largest and get smaller as ADC must have a constant input during a conversion  
the conversion proceeds. These glitches can occur at 350ns because once a bit decision is made it is locked in and can-  
intervals so an op amp with a low output impedance and fast not change.  
settling is desirable. Ultimately the input must settle to within  
the window of Figure 1 at the bit decision points in order to  
achieve 12-bit accuracy.  
32  
The HI-774 differs from the most high-speed successive  
approximation type ADC’s in that it does not require a high  
performance buffer or sample and hold. With error correction  
the input can settle while the conversion is underway, but  
only during the first 4.8µs. The input must be within 10.76%  
of the final value when the MSB decision is made. This  
occurs approximately 650ns after the conversion has been  
initiated. Digital error correction also loosens the bandwidth  
requirements of the buffer or sample and hold. As long as  
the input “kick back” disturbances settle within the window of  
Figure 1 the device will remain accurate. The combined  
effect of settling and the “kick back” disturbances must  
remain in the Figure 1 window.  
8-BIT CONVERSION  
END OF  
CONVERSION  
(12 BIT)  
16  
8
1
BIT DECISION POINTS  
± / LSB  
2
0
~ 4.8µs  
-8  
LAST BIT  
DECISION  
(12-BIT)  
-16  
MSB BIT DECISION  
~ 650ns  
12-BIT CONVERSION  
-31  
1
2
3
4
5
6
7
8
CONVERSION  
INITIATED  
TIME (µs)  
If the design is being optimized for speed, the input device  
should have closed loop bandwidth to 3MHz, and a low out-  
put impedance (calculated by dividing the open loop output  
resistance by the open loop gain). If the application requires  
a high speed sample and hold the Intersil HA-5330 or  
HA-5320 are recommended.  
FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs TIME  
STS 28  
2 12/8  
In any design the input (pin 13 or 14) should be checked  
during a conversion to make sure that the input stays within  
the correctable window of Figure 1.  
HIGH BITS  
24-27  
3
4
5
CS  
A
O
MIDDLE BITS  
20-23  
Digital Error Correction  
OFFSET  
R1  
R/C  
CE  
100K  
HI-774  
LOW BITS  
16-19  
+15V  
GAIN  
-15V  
6
The HI-774 features the smart successive approximation  
register (SSAR) which includes digital error correction. This  
has the advantage of allowing the initial input to vary within a  
+31 to -32 LSB window about the final value. The input can  
R2  
10 REF IN  
REF OUT  
100K  
100Ω  
move during the first 4.8µs, after which it must remain stable  
8
1
100Ω  
within ± / LSB. With this feature a conversion can start  
2
+5V  
1
7
before the input has settled completely; however, it must be  
within the window as described in Figure 1.  
12 BIP OFF  
13 10V  
0V TO +10V  
ANALOG  
+15V  
IN  
The conversion cycle starts by making the first 8-bit decisions  
very quickly, allowing the internal DAC to settle only to 8-bit  
INPUTS  
-15V 11  
14 20VIN€†  
0V TO +20V  
accuracy. Then the converter goes through two error correc-  
DIG COM 15  
9 ANA  
COM  
1
tion cycles. At this point the input must be stable within ± /  
2
LSB. These cycles correct the 8-bit word to 12-bit accuracy for  
any errors made (up to +16 or -32 LSBs). This is up one count  
or down two counts at 8-bit resolution. The converter then  
continues to make the 4 LSB decisions, settling out to 12-bit  
accuracy. The last four bits can adjust the code in the positive  
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.  
FIGURE 2. UNIPOLAR CONNECTIONS  
6-963  
1...9101112131415...18

中文翻译

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