HI-1567, HI-1568
March 2001
PIN CONFIGURATIONS
DESCRIPTION
The HI-1567 and HI-1568 are low power CMOS dual
transceivers designed to meet the requirements of
MIL-STD-1553 /1760 specifications.
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
1
2
3
4
5
6
7
8
9
20 TXA
The transmitter section of each channel takes
complimentary CMOS / TTL digital input data and converts
it to bi-phase Manchester encoded 1553 signals suitable
for driving the bus isolation transformer. Separate
transmitter inhibit control signals are provided for each
transmitter.
19 TXA
18 TXINHA
17 RXA
16 RXA
15 TXB
The receiver section of the each channel converts the 1553
bus bi-phase data to complimentary CMOS / TTL data
suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used to
force the output of the receiver to a logic 0 (HI-1567) or
logic 1 (HI-1568).
14 TXB
13 TXINHB
12 RXB
11 RXB
GNDB 10
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer. For designs requiring
independent access to transmitter and receiver 1553
signals, please contact your Holt Sales representative.
20 Pin Ceramic DIP package
20
19
18
17
16
15
14
13
12
1
2
VDDA
BUSA
BUSA
RXENA
GNDA
VDDB
BUSB
BUSB
RXENB
GNDB
TXA
FEATURES
TXA
3
TXINHA
RXA
!
Compliant to MIL-STD-1553A & B,
MIL-STD-1760
4
5
RXA
!
!
CMOS technology for low standby power
6
TXB
7
TXB
Smallest footprint available in 20 pin plastic
ESOIC (thermally enhanced SOIC) package
8
TXINHB
RXB
9
11 RXB
10
!
!
Less than 1.0W maximum power dissipation
20 Pin Plastic ESOIC - WB package
Available in DIP, Flatpack and small outline
(ESOIC) package options
!
!
Military processing options
Industry standard pin configurations
HOLT INTEGRATED CIRCUITS
(DS1567 Rev. B)
1
03/01