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HEF4073BPB PDF预览

HEF4073BPB

更新时间: 2024-01-13 12:01:01
品牌 Logo 应用领域
恩智浦 - NXP /
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3页 29K
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HEF4073BPB 数据手册

 浏览型号HEF4073BPB的Datasheet PDF文件第1页浏览型号HEF4073BPB的Datasheet PDF文件第2页 
Philips Semiconductors  
Product specification  
HEF4073B  
gates  
Triple 3-input AND gate  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL  
TYP.  
MAX.  
Propagation delays  
In On  
HIGH to LOW  
5
55  
25  
20  
45  
20  
15  
60  
30  
20  
60  
30  
20  
110  
50  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
23 ns  
14 ns  
12 ns  
13 ns  
9 ns  
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
10  
15  
5
tPHL  
40  
90  
LOW to HIGH  
10  
15  
5
tPLH  
tTHL  
tTLH  
40  
30  
7 ns  
Output transition times  
HIGH to LOW  
120  
60  
10 ns  
9 ns  
10  
15  
5
40  
6 ns  
120  
60  
10 ns  
9 ns  
LOW to HIGH  
10  
15  
40  
6 ns  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
10  
15  
600 fi + ∑ (foCL) × VDD  
where  
2
2700 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
2
8400 fi + ∑ (foCL) × VDD  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
VDD = supply voltage (V)  
January 1995  
3

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