HEF4072BPB

更新时间： 2024-01-19 01:30:14

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
3页	30K
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数据手册

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HEF4072BPB 数据手册

Philips Semiconductors

Product speciﬁcation

HEF4072B

gates

Dual 4-input OR gate

AC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C; C_L= 50 pF; input transition times ≤ 20 ns

V_DD

TYPICAL EXTRAPOLATION

FORMULA

SYMBOL

TYP.

MAX.

Propagation delays

I_n→ O_n

HIGH to LOW

155

53 ns + (0,55 ns/pF) C_L

24 ns + (0,23 ns/pF) C_L

17 ns + (0,16 ns/pF) C_L

48 ns + (0,55 ns/pF) C_L

24 ns + (0,23 ns/pF) C_L

17 ns + (0,16 ns/pF) C_L

10 ns + (1,0 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

10 ns + (1,0 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

t_PHL

145

LOW to HIGH

t_PLH

t_THL

t_TLH

Output transition times

HIGH to LOW

120

LOW to HIGH

V_DD

TYPICAL FORMULA FOR P (µW)

Dynamic power

dissipation per

package (P)

950 f_i+ ∑ (f_oC_L) × V_DD

where

4500 f_i+ ∑ (f_oC_L) × V_DD

f_i= input freq. (MHz)

f_o= output freq. (MHz)

C_L= load capacitance (pF)

∑ (f_oC_L) = sum of outputs

13 700 f_i+ ∑ (f_oC_L) × V_DD

V_DD= supply voltage (V)

January 1995

1 23

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