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HDMP-1636A PDF预览

HDMP-1636A

更新时间： 2024-02-03 16:09:53
品牌 Logo 应用领域
安捷伦 - AGILENT 网络接口光纤电信集成电路电信电路以太网以太网：16GBASE-T
页数 文件大小 规格书
18页 284K
描述
Gigabit Ethernet and Fibre Channel SerDes ICs

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中文翻译

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HDMP-1636A 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：10 MM, LEAD FREE, PLASTIC, QFP-64Reach Compliance Code：compliant
风险等级：5.66数据速率：1250000 Mbps
JESD-30 代码：S-PQFP-G64JESD-609代码：e3
长度：10 mm功能数量：1
端子数量：64收发器数量：1
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP64,.51SQ,20封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.45 mm子类别：Network Interfaces
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：ETHERNET TRANSCEIVER温度等级：COMMERCIAL
端子面层：MATTE TIN (394)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：10 mm
Base Number Matches：1

HDMP-1636A 数据手册

 浏览型号HDMP-1636A的Datasheet PDF文件第12页浏览型号HDMP-1636A的Datasheet PDF文件第13页浏览型号HDMP-1636A的Datasheet PDF文件第14页浏览型号HDMP-1636A的Datasheet PDF文件第15页浏览型号HDMP-1636A的Datasheet PDF文件第17页浏览型号HDMP-1636A的Datasheet PDF文件第18页 
16  
**V  
CC  
V
CC  
power supply pins of the  
HDMP-1636A/1646A/T1636A as  
shown on the schematic of Figure  
12. All bypass chip capacitors are  
C
PLLR  
0.1 µF. The V _RXA and  
CC  
V _TXA pins are the analog  
CC  
*GND  
RXCAP0  
power supply pins for the PLL  
sections. The voltage into these  
pins should be clean with  
minimum noise. The PLL loop  
filter capacitors and their pin  
locations are also shown on  
Figure 12. Notice that only two  
GND_RXTTL  
*V  
*V  
CC  
V
_RXTTL  
_RXTTL  
V
CC  
CC  
HDMP-16x6A/T1636A  
capacitors are required: C  
for  
PLLT  
CC  
TOP VIEW  
the transmitter and C  
for the  
PLLR  
V
*GND  
GND_TXA  
CC  
receiver. Nominal capacitance is  
0.1 µF. The maximum voltage  
across the capacitors is on the  
order of 1 volt, so the capacitor  
can be a low voltage type and  
physically small. The PLL  
capacitors are placed physically  
close to the appropriate pins on  
the HDMP-1636A/1646A/  
TXCAP1  
GND_RXTTL  
C
PLLT  
V
CC  
T1636A. Keeping the lines short  
will prevent them from picking  
up stray noise from surrounding  
lines or components.  
**V  
CC  
*IT IS RECOMMENDED THAT THESE PINS BE CONNECTED TO THE APPROPRIATE  
SUPPLY LINE, EITHER V OR GND, EVEN THOUGH THE PIN IS BONDED TO AN  
CC  
ISOLATED PAD. REFER TO THE I/O DEFINITIONS SECTION FOR THESE PINS FOR  
MORE DETAILS.  
** SUPPLY VOLTAGE INTO V _RXA AND V _TXA SHOULD BE FROM A LOW NOISE  
CC  
CC  
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF.  
Figure 12. Power Supply Bypass.  
Start-up Procedure:  
The transceiver start-up  
procedure(s) use the following  
Transceiver Power  
Supply Bypass and Loop  
Filter Capacitors  
conditions: V = +3.3 V ± 5%  
and REFCLK = 106.25 MHz  
(Fibre Channel)/125 MHz  
Bypass capacitors should be  
liberally used and placed as close  
as possible to the appropriate  
CC  
(Gigabit Ethernet) ± 100 ppm.  
After the above conditions have  
been met, apply valid data using a  
balanced code such as 8B/10B.  
Frequency lock occurs within  
500 µs. After frequency lock,  
phase lock occurs within 2500 bit  
times.  
1...131415161718

中文翻译

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