Datasheet > HD74SSTV16857AT

HD74SSTV16857AT

更新时间： 2024-11-23 23:55:27

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HD74SSTV16857AT 数据手册

HD74SSTV16857A

1:1 14-bit SSTL_2 Registered Buffer

ADE-205-695 (Z)

Rev.0

Jun. 2002

Description

The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and

LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is

triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to

maintain noise margins. When RESET is low, all registers are reset and all outputs are low.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held

in the low state during power up.

Features

•

Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input

Differential SSTL_2 (Stub series terminated logic) CLK signal

Flow through architecture optimizes PCB layout

Package type

TSSOP-48 pin

TVSOP-48 pin

Package code

TTP-48DBV

TTP-48DEV

Package suffix

Taping code

EL (1,000 pcs / Reel)

12 3 4 5 6 7...16

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型号	品牌	获取价格	描述	数据表
HD74SSTV16857ATEL	RENESAS	获取价格	1:1 14-bit SSTL_2 Registered Buffer
HD74SSTV16857B	RENESAS	获取价格	1:1 14-bit SSTL_2 Registered Buffer
HD74SSTV16857BNEL	RENESAS	获取价格	1:1 14-bit SSTL_2 Registered Buffer
HD74SSTV16857BTEL	RENESAS	获取价格	1:1 14-bit SSTL_2 Registered Buffer
HD74SSTV16857N	ETC	获取价格	Buffer/Driver
HD74SSTV16857NEL	RENESAS	获取价格	1:1 14-bit SSTL_2 Registered Buffer
HD74SSTV16857T	ETC	获取价格	Buffer/Driver
HD74SSTV16857TEL	RENESAS	获取价格	1:1 14-bit SSTL_2 Registered Buffer
HD74SSTV16858	ETC	获取价格	Datasheet\|ADE-205-351B\|JUN.20.01\|80K
HD74SSTV16858T	HITACHI	获取价格	D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 11-Bit, True Output, PDSO64, TS