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HD74LV573AFP PDF预览

HD74LV573AFP

更新时间: 2024-11-15 23:55:27
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
14页 68K
描述
LATCH|SINGLE|8-BIT|LV-CMOS|SOP|20PIN|PLASTIC

HD74LV573AFP 数据手册

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HD74LV573A  
Octal D-type Transparent Latches with 3-state Outputs  
ADE-205-279A (Z)  
2nd Edition  
July 1999  
Description  
The HD74LV573A has eight D-type latches with three-state outputs in a 20-pin package. When the latch  
enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D  
inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied  
to the output control input, all outputs go to a high impedance state, regardless of what signals are present at  
the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for  
the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery  
life.  
Features  
VCC = 2.0 V to 5.5 V operation  
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)  
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)  
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)  
Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)  
Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)  
Function Table  
Inputs  
OE  
L
LE  
H
H
L
D
H
L
Output Q  
H
L
L
L
X
X
Q0  
Z
H
X
Note: H:High level  
L:Low level  
X:Immaterial  
Z:High impedance  
Q0:Output level before the indicated steady state input conditions were established  

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