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HD74LS138FPEL-E PDF预览

HD74LS138FPEL-E

更新时间: 2024-12-01 21:19:15
品牌 Logo 应用领域
瑞萨 - RENESAS 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 101K
描述
IC,DECODER/DEMUX,3-TO-8-LINE,LS-TTL,SOP,16PIN,PLASTIC

HD74LS138FPEL-E 技术参数

是否Rohs认证: 符合生命周期:Not Recommended
包装说明:SOP, SOP16,.3Reach Compliance Code:compliant
风险等级:5.66JESD-30 代码:R-PDSO-G16
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.008 A
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
电源:5 V最大电源电流(ICC):10 mA
Prop。Delay @ Nom-Sup:41 ns认证状态:Not Qualified
子类别:Decoder/Drivers标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

HD74LS138FPEL-E 数据手册

 浏览型号HD74LS138FPEL-E的Datasheet PDF文件第2页浏览型号HD74LS138FPEL-E的Datasheet PDF文件第3页浏览型号HD74LS138FPEL-E的Datasheet PDF文件第4页浏览型号HD74LS138FPEL-E的Datasheet PDF文件第5页浏览型号HD74LS138FPEL-E的Datasheet PDF文件第6页浏览型号HD74LS138FPEL-E的Datasheet PDF文件第7页 
HD74LS138  
3-Line-to-8-Line Decoders / Demultiplexers  
REJ03D0434–0300  
Rev.3.00  
Jul.13.2005  
The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three  
enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when  
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one  
inverter. An enable input can be used as a data input for demultiplexing applications.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0016AE-B  
(DP-16FV)  
HD74LS138P  
DILP-16 pin  
P
-
PRSP0016DH-B  
(FP-16DAV)  
HD74LS138FPEL  
HD74LS138RPEL  
SOP-16 pin (JEITA)  
SOP-16 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0016DG-A  
(FP-16DNV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
8
16  
A
B
C
VCC  
A
Select  
Inputs  
B
C
G
Y
Y
Y
0
1
2
15  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
14  
13  
12  
11  
10  
9
2A  
G
2A  
2B  
G
2B  
1
Y
3
Outputs  
G
Enable  
Inputs  
G
Y
Y
4
5
G1  
Y
7
Outputs Y  
7
Y
6
GND  
(Top view)  
Rev.3.00, Jul.13.2005, page 1 of 7  

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