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HD74LS145FPEL PDF预览

HD74LS145FPEL

更新时间: 2024-09-21 05:35:15
品牌 Logo 应用领域
瑞萨 - RENESAS 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 88K
描述
BCD-to-Decimal Decoder / Driver (with 15 V outputs)

HD74LS145FPEL 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:SOIC包装说明:5.50 X 10.06 MM, 1.27 MM PITCH, PLASTIC, SOP-16
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
系列:LS输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:10.06 mm逻辑集成电路类型:DECIMAL DECODER/DRIVER
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:75 °C
最低工作温度:-20 °C输出特性:OPEN-COLLECTOR
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V传播延迟(tpd):50 ns
认证状态:Not Qualified座面最大高度:2.2 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL EXTENDED端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:5.5 mm
Base Number Matches:1

HD74LS145FPEL 数据手册

 浏览型号HD74LS145FPEL的Datasheet PDF文件第2页浏览型号HD74LS145FPEL的Datasheet PDF文件第3页浏览型号HD74LS145FPEL的Datasheet PDF文件第4页浏览型号HD74LS145FPEL的Datasheet PDF文件第5页浏览型号HD74LS145FPEL的Datasheet PDF文件第6页 
HD74LS145  
BCD-to-Decimal Decoder / Driver (with 15 V outputs)  
REJ03D0436–0300  
Rev.3.00  
Jul.13.2005  
This BCD-to-decimal decoder / driver consists of eight inverters and ten four-input NAND gates. The inverters are  
connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid BCD  
input logic ensures that all outputs remain off for all invalid binary input conditions. This decoder features high-  
performance, n-p-n output transistors designed for use as indicator / relay drivers or as open-collector logic-circuit  
drivers.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-16 pin  
PRDP0016AE-B  
(DP-16FV)  
HD74LS145P  
HD74LS145FPEL  
P
PRSP0016DH-B  
(FP-16DAV)  
SOP-16 pin (JEITA)  
FP  
EL (2,000 pcs/reel)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y
Y
Y
Y
Y
Y
Y
0
1
2
3
4
5
6
VCC  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
A
B
C
D
Inputs  
Outputs  
Y9  
Y8  
Y7  
Outputs  
GND  
(Top view)  
Rev.3.00, Jul.13.2005, page 1 of 5  

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