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HD74HCT620/HD74HCT623 PDF预览

HD74HCT620/HD74HCT623

更新时间: 2024-11-22 23:55:27
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其他 - ETC /
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HD74HCT620/HD74HCT623 数据手册

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HD74HCT620/HD74HCT623  
Octal Bus Transceivers (with inverted 3-state outputs)/  
Octal Bus Transceivers (with 3-state outputs)  
ADE-205-561 (Z)  
1st. Edition  
Sep. 2000  
Description  
This octal transceiver is designed for asynchronous two-way communication between data buses. The  
control function implementation allows for maximum flexibility in timng.  
This device allows data transmission from A bus to the B bus or from the B bus to the A bus depending  
upon the logic levels at the enable inputs (GBA and GAB).  
The enable inputs can be used to disable the device so that the buses are affectively isolated.  
The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of  
GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control  
inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of  
bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will  
be identical for the HD74HCT623 or complementary for the HD74HCT620.  
Features  
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility  
High Speed Operation: tpd (Bus to Bus) = 15 ns typ (CL = 50 pF)  
High Output Current: Fanout of 15 LSTTL Loads  
Wide Operating Voltage: VCC = 4.5 to 5.5 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  

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