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HD74HCT237 PDF预览

HD74HCT237

更新时间: 2024-11-05 22:55:07
品牌 Logo 应用领域
日立 - HITACHI 解码器解复用器
页数 文件大小 规格书
8页 60K
描述
3-to-8-line Decoder/Demultiplexer with Address Latch

HD74HCT237 数据手册

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HD74HCT237  
3-to-8-line Decoder/Demultiplexer with Address Latch  
Description  
The HD74HCT237 decodes a three-bit Address to one-of-eight active-high outputs. The device has a  
transparent latch for storage of the Address. Two Chip Selects, one active-low and one active-high, are  
provided to facilitate the demultiplexing, cascading, and chip-selecting functions.  
The demultiplexing function is accomplished by using the Address inputs to select the desired device  
output, and then by using one of the Chip Select as a data input while holding the other one active.  
The HD74HCT237 is the noninverting version of the HD74HCT137.  
Features  
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility  
High Speed Operation: tpd (A, B, C to Y) = 23 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 4.5 to 5.5 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  

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