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HD74AC74TELL PDF预览

HD74AC74TELL

更新时间: 2024-09-25 05:35:11
品牌 Logo 应用领域
瑞萨 - RENESAS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 121K
描述
Dual D-Type Positive Edge-Triggered Flip-Flop

HD74AC74TELL 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.06Is Samacsys:N
系列:ACJESD-30 代码:R-PDSO-G14
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:95000000 Hz
最大I(ol):0.012 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):225电源:3.3/5 V
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:125 MHzBase Number Matches:1

HD74AC74TELL 数据手册

 浏览型号HD74AC74TELL的Datasheet PDF文件第2页浏览型号HD74AC74TELL的Datasheet PDF文件第3页浏览型号HD74AC74TELL的Datasheet PDF文件第4页浏览型号HD74AC74TELL的Datasheet PDF文件第5页浏览型号HD74AC74TELL的Datasheet PDF文件第6页浏览型号HD74AC74TELL的Datasheet PDF文件第7页 
HD74AC74  
Dual D-Type Positive Edge-Triggered Flip-Flop  
REJ03D0277–0200Z  
(Previous ADE-205-361 (Z))  
Rev.2.00  
Jul.16.2004  
Description  
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs.  
Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a  
voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the  
Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be  
transferred to the outputs until the next rising edge of the Clock Pulse input.  
Features  
Asynchronous Inputs:  
Low input to S (Set) sets Q to High level  
Low input to CDD (Clear) sets Q to Low level  
Clear and Set are independent of clock  
Simultaneous Low on CD and SD makes both Q and Q High  
Outputs Source/Sink 24 mA  
Ordering Information  
Part Name  
Package Type  
Package Code Package Abbreviation Taping Abbreviation (Quantity)  
HD74AC74P  
DIP-14 pin  
DP-14, -14AV  
FP-14DAV  
P
HD74AC74FPEL  
HD74AC74RPEL  
HD74AC74TELL  
SOP-14 pin (JEITA)  
FP  
RP  
T
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
ELL (2,000 pcs/reel)  
SOP-14 pin (JEDEC) FP-14DNV  
TSSOP-14 pin TTP-14DV  
Notes: 1. Please consult the sales office for the above package availability.  
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of  
the package code.  
Pin Arrangement  
CD1  
D1  
1
2
3
4
5
6
14 VCC  
13 CD2  
12 D2  
CP1 D1  
SD1  
CD1  
CP1  
SD1  
Q1  
Q1 Q1  
11 CP2  
10 SD2  
D2  
CP2  
CD2 SD2  
Q2 Q2  
Q1  
9
8
Q2  
GND 7  
Q2  
(Top view)  
Rev.2.00, Jul.16.2004, page 1 of 7  

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