HD74ACT107

更新时间： 2024-11-12 22:55:03

品牌	Logo	应用领域
日立 - HITACHI		触发器时钟
页数	文件大小	规格书
10页	60K
描述
Dual JK Flip-Flop (with Separate Clear and Clock)

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HD74ACT107 数据手册

HD74AC107/HD74ACT107

Dual JK Flip-Flop (with Separate Clear and Clock)

Description

The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.

Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the

coupling transistors which connect the master and slave sections. The sequence of operation is as follows:

1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;

4) transfer information from master to slave.

Features

•

Outputs Source/Sink 24 mA

HD74ACT107 has TTL-Compatible Inputs

Pin Arrangement

J₁

K₁

Q₂

14 V_CC

13 C_D1

12 CP₁

11 K₂

10 C_D2

CP₂

GND 7

J₂

(Top view)

12 3 4 5 6 7...10

中文翻译

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型号	品牌	获取价格	描述	数据表
HD74ACT107FP	ETC	获取价格	J-K-Type Flip-Flop
HD74ACT107FPEL	RENESAS	获取价格	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, SOP-
HD74ACT107FPVEL	RENESAS	获取价格	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, LEAD
HD74ACT107P	HITACHI	获取价格	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, DP-1
HD74ACT107RP	ETC	获取价格	FLIP-FLOP\|DUAL\|J/K TYPE\|ACT-CMOS\|SOP\|14PIN\|PLASTIC
HD74ACT107RPEL	RENESAS	获取价格	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, SOP-
HD74ACT107RP-EL	HITACHI	获取价格	暂无描述
HD74ACT107RPVEL	RENESAS	获取价格	ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, LEAD
HD74ACT107T	RENESAS	获取价格	暂无描述
HD74ACT107T	HITACHI	获取价格	J-K Flip-Flop, ACT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C